Pulse-Modulated Plasma Etching of Copper Thin Films via CH3COOH/Ar

Pulse-modulated plasma etching of copper masked using SIO2 films was conducted via a CH3COOH/Ar. The etch characteristics were examined under pulse-modulated plasma. As the duty ratio of pulse decreased and the frequency of pulse increased, the etch selectivity and etch profile were improved. X-ray photoelectron spectroscopy and indicated that more copper oxides (Cu2O and CuO) and Cu(CH3COO)2 were formed using pulse-modulated plasma than those formed using continuous-wave (CW) plasma. As the concentration of CH3COOH gas in pulse-modulated plasma increased, the formation of these copper compounds increased, which improved the etch profiles. Optical emission spectroscopy confirmed that the active ingredients of the plasma increased with decreasing pulse duty ratio and increasing frequency. Therefore, the optimized pulsed plasma etching of copper via a CH3COOH/Ar gas provides better etch profile than that by CW plasma etching.

Development of Virtual Metrology Using Plasma Information Variables to Predict Si Etch Profile Processed by SF6/O2/Ar Capacitively Coupled Plasma

In the semiconductor etch process, as the critical dimension (CD) decreases and the difficulty of the process control increases, in-situ and real-time etch profile monitoring becomes important. It leads to the development of virtual metrology (VM) technology, one of the measurement and inspection (MI) technology that predicts the etch profile during the process. Recently, VM to predict the etch depth using plasma information (PI) variables and the etch process data based on the statistical regression method had been developed and demonstrated high performance. In this study, VM using PI variables, named PI-VM, was extended to monitor the etch profile and investigated the role of PI variables and features of PI-VM. PI variables are obtained through analysis on optical emission spectrum data. The features in PI-VM are investigated in terms of plasma physics and etch kinetics. The PI-VM is developed to monitor the etch depth, bowing CD, etch depth times bowing CD (rectangular model), and etch area model (non-rectangular model). PI-VM for etch depth and bowing CD showed high prediction accuracy of R-square value (R2) 0.8 or higher. The rectangular and non-rectangular etch area model PI-VM showed prediction accuracy R2 of 0.78 and 0.49, respectively. The first trial of virtual metrology to monitor the etch profile will contribute to the development of the etch profile control technology.

Etch Characteristics of Nanoscale Patterned Magnetic Tunnel Junction Stacks Using Pulse-Modulated Radio Frequency Source Plasma

Magnetic tunnel junctions (MTJs) patterned with 70 × 70 nm2 square arrays were etched in a CH4/O2/Ar gas mixture by pulse-modulated inductively coupled plasma reactive ion etching (ICPRIE). A good etch profile of MTJs with etch slope of approximately 82° was achieved by adjusting the on–off duty ratio of the plasma and pulse frequency. Langmuir probe analysis and optical emission spectroscopy confirmed that the balance between the formation of the passivation layer as an etch byproduct and sputtering effect is responsible for the etch selectivity and etch profile with a high degree of anisotropy. It is concluded that the application of pulse-modulated plasma on ICPRIE can be an effective method to obtain the anisotropic etch profile of nanometer-scale MTJs.

Etch characteristics of nanoscale ultra low-k dielectric using C3H2F6

Next generation semiconductor devices require ultra low dielectric constant (ULK) materials such as porous SiCOH on the back end of line structure for lower resistance and capacitance (RC) time delay, however, these ULK materials are easily damaged by the exposure to plasmas during the etching. In this study, etch characteristics of nanoscale TiN masked porous SiCOH such as etch rate, etch profile, surface damage, etc. and plasma characteristics by using C3H2F6 based gases have been investigated with a dual-frequency capacitively coupled plasma system (DF-CCP) and the results were compared with those by using conventional C4F8 based gases used for low-k dielectric etching. The results showed that, for the similar etch rates and etch profiles of porous SiCOH, lower sidewall damage was observed for the etching with the C3H2F6 compared to the C4F8. The analysis showed that it was related to less UV (less than 400 nm) emission and less fluorine radicals in the plasma for C3 H2F6 compared to C4F8, which leads to less fluorine diffusion to the sidewall surface of the etched porous SiCOH by the fluorine scavenging by hydrogen in C3H2F6.

Optimization of Cupric Chloride Subtractive Etching for Cu High Density Interconnects

The continuously increasing demand for innovation in the miniaturization of microelectronics has driven the need for ever more precise fabrication strategies for device packaging, especially for printed circuit boards (PCBs). Subtractive copper etching is a fundamental step in this processes, requiring very precise control of etch rate and etch profile. Cu etching baths are typically monitored with several parameters including oxidation-reduction potential, conductivity, and specific gravity. However, the etch rate and etch profile can be difficult to control even under strict engineering controls of those monitoring parameters. The mechanism of acidic cupric chloride etching, regeneration and recovery is complex, and the current monitoring strategies can have difficulty controlling the complex interlocking chemical equilibria. We report that thin-film UV-Vis spectroscopy has the capability to effectively monitor the complex changes to the etch bath. UV-Vis also reveals various underlying mechanism reasons for etch bath behavior and illuminates the roles of H+ and Cl− to the etch bath while also providing a means to monitor the Cl−. Furthermore, UV-Vis can be utilized to improve current monitoring strategies, as it can identify and predict etching behavior that the current standard methodologies may have difficulty predicting.

Wafer Thinning for Advanced Packaging Applications

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.