silicon trenches
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Universe ◽  
2021 ◽  
Vol 7 (4) ◽  
pp. 93
Author(s):  
Giuseppe Bimonte ◽  
Benjamin Spreng ◽  
Paulo A. Maia Neto ◽  
Gert-Ludwig Ingold ◽  
Galina L. Klimchitskaya ◽  
...  

We present results on the determination of the differential Casimir force between an Au-coated sapphire sphere and the top and bottom of Au-coated deep silicon trenches performed by means of the micromechanical torsional oscillator in the range of separations from 0.2 to 8 μm. The random and systematic errors in the measured force signal are determined at the 95% confidence level and combined into the total experimental error. The role of surface roughness and edge effects is investigated and shown to be negligibly small. The distribution of patch potentials is characterized by Kelvin probe microscopy, yielding an estimate of the typical size of patches, the respective r.m.s. voltage and their impact on the measured force. A comparison between the experimental results and theory is performed with no fitting parameters. For this purpose, the Casimir force in the sphere-plate geometry is computed independently on the basis of first principles of quantum electrodynamics using the scattering theory and the gradient expansion. In doing so, the frequency-dependent dielectric permittivity of Au is found from the optical data extrapolated to zero frequency by means of the plasma and Drude models. It is shown that the measurement results exclude the Drude model extrapolation over the region of separations from 0.2 to 4.8 μm, whereas the alternative extrapolation by means of the plasma model is experimentally consistent over the entire measurement range. A discussion of the obtained results is provided.


2020 ◽  
Vol 6 (1) ◽  
Author(s):  
Federico Ribet ◽  
Xiaojing Wang ◽  
Miku Laakso ◽  
Simone Pagliano ◽  
Frank Niklaus ◽  
...  

AbstractThe out-of-plane integration of microfabricated planar microchips into functional three-dimensional (3D) devices is a challenge in various emerging MEMS applications such as advanced biosensors and flow sensors. However, no conventional approach currently provides a versatile solution to vertically assemble sensitive or fragile microchips into a separate receiving substrate and to create electrical connections. In this study, we present a method to realize vertical magnetic-field-assisted assembly of discrete silicon microchips into a target receiving substrate and subsequent electrical contacting of the microchips by edge wire bonding, to create interconnections between the receiving substrate and the vertically oriented microchips. Vertical assembly is achieved by combining carefully designed microchip geometries for shape matching and striped patterns of the ferromagnetic material (nickel) on the backside of the microchips, enabling controlled vertical lifting directionality independently of the microchip’s aspect ratio. To form electrical connections between the receiving substrate and a vertically assembled microchip, featuring standard metallic contact electrodes only on its frontside, an edge wire bonding process was developed to realize ball bonds on the top sidewall of the vertically placed microchip. The top sidewall features silicon trenches in correspondence to the frontside electrodes, which induce deformation of the free air balls and result in both mechanical ball bond fixation and around-the-edge metallic connections. The edge wire bonds are realized at room temperature and show minimal contact resistance (<0.2 Ω) and excellent mechanical robustness (>168 mN in pull tests). In our approach, the microchips and the receiving substrate are independently manufactured using standard silicon micromachining processes and materials, with a subsequent heterogeneous integration of the components. Thus, this integration technology potentially enables emerging MEMS applications that require 3D out-of-plane assembly of microchips.


2019 ◽  
Vol 2 (2) ◽  
pp. 363-374 ◽  
Author(s):  
Timo Mueller ◽  
Dirk Dantz ◽  
Wilfried von Ammon ◽  
Janis Virbulis ◽  
Uldis Bethers

2019 ◽  
Vol 2019 ◽  
pp. 1-10
Author(s):  
Jiale Su ◽  
Xinwei Zhang ◽  
Guoping Zhou ◽  
Jianjian Gu ◽  
Changfeng Xia ◽  
...  

This paper presents a piezoresistive barometric pressure sensor fabricated by using a Silicon-on-Nothing (SON) technology. Array of silicon trenches were annealed in hydrogen environment to form continuing crystalline silicon membrane over a vacuum cavity. Epitaxial growth on the silicon membrane is then completed for the desired thickness. All processes are CMOS compatible and performed on the front side of the silicon wafer. The piezoresistive barometric pressure sensor has been demonstrated with pressure hysteresis as low as 0.007%.


2018 ◽  
Vol 27 (01n02) ◽  
pp. 1840002 ◽  
Author(s):  
Machhindra Koirala ◽  
Jia Woei Wu ◽  
Adam Weltz ◽  
Rajendra Dahal ◽  
Yaron Danon ◽  
...  

We present a cost effective and scalable approach to fabricate solid state thermal neutron detectors. Electrophoretic deposition technique is used to fill deep silicon trenches with 10B nanoparticles instead of conventional chemical vapor deposition process. Deep silicon trenches with width of 5-6 μm and depth of 60-65 μm were fabricated in a p-type Si (110) wafer using wet chemical etching method instead of DRIE method. These silicon trenches were converted into continuous p-n junction by the standard phosphorus diffusion process. 10B micro/nano particle suspension in ethyl alcohol was used for electrophoretic deposition of particles in deep trenches and iodine was used to change the zeta potential of the particles. The measured effective boron nanoparticles density inside the trenches was estimated to be 0.7 gm cm-3. Under the self-biased condition, the fabricated device showed the intrinsic thermal neutron detection efficiency of 20.9% for a 2.5 × 2.5 mm2 device area.


2017 ◽  
Vol 110 (19) ◽  
pp. 192105 ◽  
Author(s):  
Jia-Woei Wu ◽  
Adam Weltz ◽  
Machhindra Koirala ◽  
James J.-Q. Lu ◽  
Rajendra Dahal ◽  
...  

2015 ◽  
Vol 14 (2) ◽  
pp. 021104 ◽  
Author(s):  
Ahmad Faridian ◽  
Valeriano Ferreras Paz ◽  
Karsten Frenner ◽  
Giancarlo Pedrini ◽  
Arie Den Boef ◽  
...  

2014 ◽  
Vol 219 ◽  
pp. 32-35
Author(s):  
Philippe Garnier ◽  
Nathalie Drogue ◽  
Romain Duru

Metal contamination impact on transistors’ degradation has been widely studied. Nonetheless, most of the work has been performed on blanket wafers, or based on punctual yield crisis during the integrated circuits’ manufacturing. This paper proposes a comparison of the contamination and metals removal efficiency between blanket wafers and inside deep silicon trenches.


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