Two phase nonoverlapping clocked All-N-Logic in subthreshold region with 49fJ power delay product

2012 ◽  
Author(s):  
M. Kargar ◽  
M. B. Ghaznavi-Ghoushchi
Keyword(s):  
Two Phase ◽  
Subthreshold Region ◽  
Power Delay Product

scholarly journals Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
‘Aqilah binti Abdul Tahrim ◽  
Huei Chaeng Chin ◽  
Cheng Siong Lim ◽  
Michael Loong Peng Tan
Keyword(s):  
High Speed ◽  
Average Power ◽  
Full Adder ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Subthreshold Region ◽  
And Performance ◽  
Power Delay Product ◽  
20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

scholarly journals 9T Full Adder Design in Subthreshold Region

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-5 ◽  
Author(s):  
Shiwani Singh ◽  
Tripti Sharma ◽  
K. G. Sharma ◽  
B. P. Singh
Keyword(s):  
Standard Model ◽  
Energy Efficient ◽  
Full Adder ◽  
Viable Option ◽  
Subthreshold Region ◽  
Ultralow Power ◽  
Power Delay Product ◽  
Power And Energy

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45 nm standard model on Tanner EDA tool version 13.0.

scholarly journals Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications

2021 ◽  
Author(s):  
Shahin S. Lotfabadi
Keyword(s):  
Power Efficiency ◽  
Biomedical Applications ◽  
Supply Voltage ◽  
Low Frequency ◽  
Normal Operation ◽  
Subthreshold Region ◽  
Design Constraint ◽  
Saturation Region ◽  
And Performance ◽  
Power Delay Product

Power is a significant design constraint for implementing portable applications. Operating transistors in the subthreshold region can significantly reduce power consumption while reducing performance. The low frequency nature of biosignals makes a FPGA operating subthreshold region a good candidate. In this work, I investigate the feasibility of desinging such a device and the trade-off between power consumpation and performance for FPGA routing resources operating in the subthreshold region. For the 32nm Predictive Technology Model studied in this work, it was observed a power reduction of 197.7 times (or power-delay-product reduction of 3.3 times) for operating under a supply voltage of 0.4 volts (as compared to normal operation in the saturation region using a 0.9V). Under a supply voltage of 0,4 volts, FPGA can operate at 2.0 MHz while allowing signals to propagate unregistered through 20 routing tracks which meets the real-time requirement for processing 20000 samples per second.

scholarly journals Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications

2021 ◽  
Author(s):  
Shahin S. Lotfabadi
Keyword(s):  
Power Efficiency ◽  
Biomedical Applications ◽  
Supply Voltage ◽  
Low Frequency ◽  
Normal Operation ◽  
Subthreshold Region ◽  
Design Constraint ◽  
Saturation Region ◽  
And Performance ◽  
Power Delay Product

Power is a significant design constraint for implementing portable applications. Operating transistors in the subthreshold region can significantly reduce power consumption while reducing performance. The low frequency nature of biosignals makes a FPGA operating subthreshold region a good candidate. In this work, I investigate the feasibility of desinging such a device and the trade-off between power consumpation and performance for FPGA routing resources operating in the subthreshold region. For the 32nm Predictive Technology Model studied in this work, it was observed a power reduction of 197.7 times (or power-delay-product reduction of 3.3 times) for operating under a supply voltage of 0.4 volts (as compared to normal operation in the saturation region using a 0.9V). Under a supply voltage of 0,4 volts, FPGA can operate at 2.0 MHz while allowing signals to propagate unregistered through 20 routing tracks which meets the real-time requirement for processing 20000 samples per second.

DESIGN OF LOW POWER TWO-PHASE CMOS BUFFER FOR LARGE CAPACITIVE LOADING APPLICATIONS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250092
Author(s):  
HUNG-YI LIN ◽  
YEN-TAI LAI
Keyword(s):  
Theoretical Analysis ◽  
Low Power ◽  
Power Dissipation ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Two Phase ◽  
Tapered Chains ◽  
Capacitive Loading ◽  
Power Delay Product ◽  
Circuit Power

In this paper, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for non-speed-critical large capacitive loading applications is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer's output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer. Moreover, the overall power dissipation of the proposed buffer is further decreased by optimizing the number of tapered stages and the values of tapered factors in the tapered chains of the short-circuit power eliminating circuit. In order to validate the efficiency of the proposed design, theoretical analysis and simulations with various capacitive loads are conducted using TSMC 0.18-μm 1P6M and UMC advanced 90-nm 1P9M CMOS technologies. The results show that the power dissipation of the proposed two-phase CMOS buffer is 8.6% lower than that of the conventional two-phase CMOS tapered buffer. The power-delay product of the proposed buffer is 2.7% smaller than that of the conventional tapered buffer.

Effect of Shock Loading on the Microstructure of Uniloy 326

1974 ◽  
Vol 32 ◽  
pp. 504-505
Author(s):  
K. P. Staudhammer ◽  
L. E. Murr
Keyword(s):  
Grain Size ◽  
Shock Loading ◽  
Current Investigation ◽  
Two Phase ◽  
05 C ◽  
Shock Deformation ◽  
Heat Treated

The effect of shock loading on a variety of steels has been reviewed recently by Leslie. It is generally observed that significant changes in microstructure and microhardness are produced by explosive shock deformation. While the effect of shock loading on austenitic, ferritic, martensitic, and pearlitic structures has been investigated, there have been no systematic studies of the shock-loading of microduplex structures.In the current investigation, the shock-loading response of millrolled and heat-treated Uniloy 326 (thickness 60 mil) having a residual grain size of 1 to 2μ before shock loading was studied. Uniloy 326 is a two phase (microduplex) alloy consisting of 30% austenite (γ) in a ferrite (α) matrix; with the composition.3% Ti, 1% Mn, .6% Si,.05% C, 6% Ni, 26% Cr, balance Fe.

Exsolution and inversion in pigeonite from the Whin Sill, Northern England

1978 ◽  
Vol 36 (1) ◽  
pp. 474-475
Author(s):  
P.P.K. Smith
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Homogeneous Nucleation ◽  
Silicate Mineral ◽  
Antiphase Boundaries ◽  
Two Phase ◽  
Primitive Form ◽  
The Core ◽  
Nucleation Mechanisms ◽  
And Inversion

Grains of pigeonite, a calcium-poor silicate mineral of the pyroxene group, from the Whin Sill dolerite have been ion-thinned and examined by TEM. The pigeonite is strongly zoned chemically from the composition Wo8En64FS28 in the core to Wo13En34FS53 at the rim. Two phase transformations have occurred during the cooling of this pigeonite:- exsolution of augite, a more calcic pyroxene, and inversion of the pigeonite from the high- temperature C face-centred form to the low-temperature primitive form, with the formation of antiphase boundaries (APB's). Different sequences of these exsolution and inversion reactions, together with different nucleation mechanisms of the augite, have created three distinct microstructures depending on the position in the grain.In the core of the grains small platelets of augite about 0.02μm thick have farmed parallel to the (001) plane (Fig. 1). These are thought to have exsolved by homogeneous nucleation. Subsequently the inversion of the pigeonite has led to the creation of APB's.

Shock consolidation of Ni-Ti alloy powder

1986 ◽  
Vol 44 ◽  
pp. 430-431
Author(s):  
Naresh N. Thadhani ◽  
Thad Vreeland ◽  
Thomas J. Ahrens
Keyword(s):  
Alloy Powder ◽  
Amorphous Material ◽  
Ti Alloy ◽  
Two Phase ◽  
Near Surface ◽  
Optical Micrograph ◽  
Shock Compaction ◽  
Powder Particles ◽  
Ti Powder ◽  
Rapidly Solidified

A spherically-shaped, microcrystalline Ni-Ti alloy powder having fairly nonhomogeneous particle size distribution and chemical composition was consolidated with shock input energy of 316 kJ/kg. In the process of consolidation, shock energy is preferentially input at particle surfaces, resulting in melting of near-surface material and interparticle welding. The Ni-Ti powder particles were 2-60 μm in diameter (Fig. 1). About 30-40% of the powder particles were Ni-65wt% and balance were Ni-45wt%Ti (estimated by EMPA).Upon shock compaction, the two phase Ni-Ti powder particles were bonded together by the interparticle melt which rapidly solidified, usually to amorphous material. Fig. 2 is an optical micrograph (in plane of shock) of the consolidated Ni-Ti alloy powder, showing the particles with different etching contrast.

A Comparison of Tem and Apfim to the Interpretation of Modulated Microstructures

1985 ◽  
Vol 43 ◽  
pp. 70-71
Author(s):  
M.G. Burke ◽  
M.K. Miller
Keyword(s):  
Low Temperature ◽  
Microstructural Characterization ◽  
Superlattice Reflection ◽  
High Volume ◽  
Atom Probe ◽  
Dark Field ◽  
Miscibility Gap ◽  
Second Phase ◽  
Two Phase ◽  
Probe Field

Interpretation of fine-scale microstructures containing high volume fractions of second phase is complex. In particular, microstructures developed through decomposition within low temperature miscibility gaps may be extremely fine. This paper compares the morphological interpretations of such complex microstructures by the high-resolution techniques of TEM and atom probe field-ion microscopy (APFIM).The Fe-25 at% Be alloy selected for this study was aged within the low temperature miscibility gap to form a <100> aligned two-phase microstructure. This triaxially modulated microstructure is composed of an Fe-rich ferrite phase and a B2-ordered Be-enriched phase. The microstructural characterization through conventional bright-field TEM is inadequate because of the many contributions to image contrast. The ordering reaction which accompanies spinodal decomposition in this alloy permits simplification of the image by the use of the centered dark field technique to image just one phase. A CDF image formed with a B2 superlattice reflection is shown in fig. 1. In this CDF micrograph, the the B2-ordered Be-enriched phase appears as bright regions in the darkly-imaging ferrite. By examining the specimen in a [001] orientation, the <100> nature of the modulations is evident.

A TEM study of the influence of microstructure on the superplastic behavior of a U-5.8 wt.% Nb alloy

1986 ◽  
Vol 44 ◽  
pp. 568-569
Author(s):  
G. Mackiewicz Ludtka
Keyword(s):  
Grain Size ◽  
Heating Rate ◽  
Phase Field ◽  
Single Phase ◽  
Superplastic Behavior ◽  
Two Phase ◽  
Single Phase Field

Historically, metals exhibit superplasticity only while forming in a two-phase field because a two-phase microstructure helps ensure a fine, stable grain size. In the U-5.8 Nb alloy, superplastici ty exists for up to 2 h in the single phase field (γ1) at 670°C. This is above the equilibrium monotectoid temperature of 647°C. Utilizing dilatometry, the superplastic (SP) U-5.8 Nb alloy requires superheating to 658°C to initiate the α+γ2 → γ1 transformation at a heating rate of 1.5°C/s. Hence, the U-5.8 Nb alloy exhibits an anomolous superplastic behavior.

Sign in / Sign up

Export Citation Format

Share Document