Modeling the Effects of Interface Traps on Scanning Capacitance Microscopy dC/dV Measurement

Abstract By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

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Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0102 ◽

2006 ◽

Author(s):

J.S. McMurray ◽

C.M. Molella

Keyword(s):

The Body ◽

Silicon On Insulator ◽

Back Side ◽

Cross Sectional ◽

Plan View ◽

Spreading Resistance ◽

Scanning Capacitance Microscopy ◽

Root Cause ◽

Cross Sectional Imaging ◽

Active Channel

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

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Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0094 ◽

2006 ◽

Author(s):

Vinod Narang ◽

P. Muthu ◽

J.M. Chin ◽

Vanissa Lim

Keyword(s):

Plasma Etching ◽

Data Interpretation ◽

Parameters Optimization ◽

Scanning Capacitance Microscopy ◽

Microscopy Technique ◽

Thermal Oxide ◽

Specific Analysis ◽

Thin Oxide ◽

P Type ◽

Uv Ozone

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

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Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0205 ◽

2014 ◽

Author(s):

Yuk L. Tsang ◽

Alex VanVianen ◽

Xiang D. Wang ◽

N. David Theodore

Keyword(s):

Threshold Voltage ◽

Crystalline Silicon ◽

Electrical Characterization ◽

Visual Defect ◽

Scanning Capacitance Microscopy ◽

Device Model ◽

Graphical Simulation ◽

Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

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Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

10.31399/asm.cp.istfa2018p0543 ◽

2018 ◽

Author(s):

Lucile C. Teague Sheridan ◽

Tanya Schaeffer ◽

Yuting Wei ◽

Satish Kodali ◽

Chong Khiam Oh

Keyword(s):

Atomic Force Microscopy ◽

Failure Analysis ◽

Fault Isolation ◽

Scanning Capacitance Microscopy ◽

Force Microscopy ◽

Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

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Calculation of lateral distribution of interface traps along MIS channel

Electronics Letters ◽

10.1049/el:19910906 ◽

1991 ◽

Vol 27 (16) ◽

pp. 1445 ◽

Cited By ~ 2

Author(s):

A.K. Henning ◽

J.A. Dimauro

Keyword(s):

Lateral Distribution ◽

Interface Traps

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