Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

2006 ◽  
Author(s):  
Vinod Narang ◽  
P. Muthu ◽  
J.M. Chin ◽  
Vanissa Lim
Keyword(s):  
Plasma Etching ◽  
Data Interpretation ◽  
Parameters Optimization ◽  
Scanning Capacitance Microscopy ◽  
Microscopy Technique ◽  
Thermal Oxide ◽  
Specific Analysis ◽  
Thin Oxide ◽  
P Type ◽  
Uv Ozone

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

UV–ozone precleaning and forming gas annealing applied to wet thermal oxidation of p-type silicon carbide

1999 ◽  
Vol 2 (1) ◽  
pp. 23-27 ◽  
Author(s):  
Carl-Mikael Zetterling ◽  
Mikael Östling ◽  
Chris I Harris ◽  
Peter C Wood ◽  
S.Simon Wong
Keyword(s):  
Silicon Carbide ◽  
Thermal Oxidation ◽  
Type Silicon ◽  
P Type ◽  
Uv Ozone

Flat-band Voltage Study Of Atomic-layer-Deposited Aluminum-oxide Subjected To Spike Thermal Annealing

2003 ◽  
Vol 765 ◽  
Author(s):  
V. R. Mehta ◽  
A. T. Fiory ◽  
N. M. Ravindra ◽  
M. Y. Ho ◽  
G. D. Wilk ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Oxide Thickness ◽  
Atomic Diffusion ◽  
Flat Band ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Thermal Oxide ◽  
P Type ◽  
Low Thermal Budget ◽  
Spike Annealing

AbstractHigh-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N2 ambient at 800°C for 30 s, or spike annealed at 950, 1000, and 1050°C (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800°C anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in VFB were observed, relative to a pure SiO2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the VFB shift for ALD films deposited over underlayer films. The VFB shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.

Dry Etch Damage in GaAs P-N Junctions

1991 ◽  
Vol 240 ◽  
Author(s):  
S. J. Pearton ◽  
F. Ren ◽  
C. R. Abernathy ◽  
T. R. Fullowan ◽  
J. R. Lothian
Keyword(s):  
Plasma Etching ◽  
Ion Bombardment ◽  
Plasma Exposure ◽  
Base Resistance ◽  
Ion Energy ◽  
Ion Energies ◽  
A Minor ◽  
P Type ◽  
Dry Etch ◽  
Very High

ABSTRACTGaAs p-n junction mesa-diode structures were fabricated so that both n- and p-type layers could be simultaneously exposed to either O2 or H2 discharges. This simulates the ion bombardment during plasma etching with either CCl2F2/O2 or CH4/H2 mixtures. The samples were exposed to 1 mTorr discharges for period of 1–20 min with DC biases of -25 to -400V on the cathode. For O2 ion bombardment, the collector resistance showed only minor (≤10%) increases for biases up to -200 V and more rapid increases thereafter. In our structure, this indicates that bombardment-induced point defects penetrate at least 500 Å of GaAs for ion energies of ≥200eV. The base resistance displayed only a minor increase (∼10%) over the pre-exposure value even for O+ ion energies of 375 eV, due to the very high doping (1020 cm−3 ) in the base. More significant increases in both collector and base resistances were observed for hydrogen ion bombardment due to hydrogen passivation effects. We will give details of this behaviour as a function of ion energy, plasma exposure time and post-treatment annealing temperature.

Comparison of Electrical Behavior of GaN-Based MOS Structures Obtained by Different PECVD Process

2012 ◽  
Vol 711 ◽  
pp. 228-232
Author(s):  
Elias Al Alam ◽  
Ignasi Cortés ◽  
T. Begou ◽  
Antoine Goullet ◽  
Frederique Morancho ◽  
...  
Keyword(s):  
Surface Preparation ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Plasma Oxidation ◽  
Interface Quality ◽  
Mos Capacitors ◽  
Dielectric Thin Film ◽  
P Type ◽  
Mos Structures ◽  
Uv Ozone

MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuousICPPECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.

Semi-automatic, volume production of silicon solar cells

1987 ◽  
Vol 65 (8) ◽  
pp. 892-896 ◽  
Author(s):  
R. E. Thomas ◽  
C. E. Norman ◽  
S. Varma ◽  
G. Schwartz ◽  
E. M. Absi
Keyword(s):  
Solar Cells ◽  
Single Crystal ◽  
Plasma Etching ◽  
Low Cost ◽  
Single Crystal Silicon ◽  
High Yield ◽  
Silicon Solar Cells ◽  
Crystal Silicon ◽  
Volume Production ◽  
P Type

A low-cost, high-yield technology for producing single-crystal silicon solar cells at high volumes, and suitable for export to developing countries, is described. The process begins with 100 mm diameter as-sawn single-crystal p-type wafers with one primary flat. Processing steps include etching and surface texturization, gaseous-source diffusion, plasma etching, and contacting via screen printing. The necessary adaptations of such standard processes as diffusion and plasma etching to solar-cell production are detailed. New process developments include a high-throughput surface-texturization technique, and automatic printing and firing of cell contacts.The technology, coupled with automated equipment developed specifically for the purpose, results in solar cells with an average efficiency greater than 12%, a yield exceeding 95%, a tight statistical spread on parameters, and a wide tolerance to starting substrates (including the first 100 mm diameter wafers made in Canada). It is shown that with minor modifications, the present single shift 500 kWp (kilowatt peak) per year capacity technology can be readily expanded to 1 MWp per year, adapted to square and polycrystalline substrates, and efficiencies increased above 13%.

A Semiconductor Nano-Patterning Approach Using AFM-Scratching Through Oxide Thin Layers

2002 ◽  
Vol 740 ◽  
Author(s):  
L. Santinacci ◽  
T. Djenizian ◽  
P. Schmuki
Keyword(s):  
Oxide Layer ◽  
Electrochemical Deposition ◽  
Thin Layers ◽  
Native Oxide ◽  
Silicon Substrates ◽  
Native Oxide Layer ◽  
Thermal Oxide ◽  
P Type ◽  
Insulating Properties ◽  
Nano Patterning

ABSTRACTAFM-scratching was performed through thin oxide layer which was either a native oxide layer (1.5 – 2 nm thick) or a thermal oxide layer (10 nm thick). Due to their insulating properties, the SiO2 films act as masks for the metal electrochemical deposition. In the scratched openings copper deposition can take place selectively and thus nano-scale metal lines could be successfully plated onto the p-type silicon substrates. Using particularly, if sufficiently thick thermal oxide has advantages over the native oxide, it allows a H-termination of the Si within the grooves (HF treatment) without eliminating the oxide layer on the rest of the surface.

An Investigation of Scanning Capacitance Microscopy on Iron-Contaminated p-Type Silicon

2001 ◽  
Vol 4 (9) ◽  
pp. G69 ◽  
Author(s):  
M. N. Chang ◽  
T. Y. Chang ◽  
F. M. Pan ◽  
B. W. Wu ◽  
T. F. Lei
Keyword(s):  
Scanning Capacitance Microscopy ◽  
Type Silicon ◽  
P Type
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