The precise measurement of phase noise of ultra-low-noise stable oscillators and frequency synthesizers under vibration and acoustic noise conditions

Author(s):  
V.I. Sidko ◽  
V.A. Khitrovsky
2020 ◽  
pp. 51-56
Author(s):  
Vladimir V. Romashov ◽  
Kirill A. Yakimenko ◽  
Andrey N. Doktorov ◽  
Lubov V. Romashova

The research of the possibility of using hybrid frequency synthesizers based on direct digital and direct analog methods of frequency synthesis as heterodynes of modern spectrum analyzers constructed according to the superheterodyne scheme is presented. The main advantages of such synthesizers over traditionally used heterodyne schemes based on direct digital and indirect frequency synthesis methods are shown. The requirements for the heterodynes of the first mixing stages of spectrum analyzers are presented. A block diagram of a wideband heterodyne generating a frequency range from 4000 MHz to 8000 MHz with a step not exceeding 1 Hz is proposed. Formulas for calculating the main frequency ratios in the structure of the heterodyne have been developed. A mathematical model of phase noise power spectral density (PSD) depending on the offset frequency from the carrier is developed. The noise characteristics of the proposed scheme are studied using the model. It is determined that at the output frequency of the heterodyne equal to 4521,4 MHz, the level of phase noise PSD is: minus 90 dBc/Hz at the offset frequency equal to 100 Hz; minus 140 dBc/Hz at the offset frequency equal to 100 kHz. It is shown that the hybrid synthesizer based on direct digital and direct analog synthesis methods has an advantage in the level of phase noise from 5 to 30 dB over the low-noise heterodynes of modern spectrum analyzers at frequencies above 1 kHz from the carrier. Additional advantages of the proposed scheme are a simple architecture, low power consumption and high frequency tuning speed due to the absence of phaselocked loops in the structure of the heterodyne.


Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 


2021 ◽  
Vol 42 (4) ◽  
pp. 469-472
Author(s):  
Yingtao Yu ◽  
Si Chen ◽  
Qitao Hu ◽  
Paul Solomon ◽  
Zhen Zhang

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