Mechanism of I–V asymmetry of MIM capacitors based on high-k dielectric

Author(s):  
W.S. Lau ◽  
D.Q. Yu ◽  
X. Wang ◽  
H. Wong ◽  
Y. Xu
2007 ◽  
Vol 134 ◽  
pp. 379-382
Author(s):  
Claire Therese Richard ◽  
D. Benoit ◽  
S. Cremer ◽  
L. Dubost ◽  
B. Iteprat ◽  
...  

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.


2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


2012 ◽  
Vol 29 (5) ◽  
pp. 057702 ◽  
Author(s):  
Yue-Chan Kong ◽  
Fang-Shi Xue ◽  
Jian-Jun Zhou ◽  
Liang Li ◽  
Chen Chen ◽  
...  

2012 ◽  
Vol 45 (3) ◽  
pp. 537-542 ◽  
Author(s):  
C.-Y. Wu ◽  
P.-Y. Hsu ◽  
C. L. Wang ◽  
T.-C. Liao ◽  
H.-C. Cheng ◽  
...  

2017 ◽  
Vol 897 ◽  
pp. 571-574 ◽  
Author(s):  
Vidya Naidu ◽  
Sivaprasad Kotamraju

Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO2 and ZrO2 are investigated. SiC IGBT with HfO2 and ZrO2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration.


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