Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications

2002 ◽  
Author(s):  
K. Amir ◽  
B. Eric
Keyword(s):  
Error Correcting Codes ◽  
System Level ◽  
Decoding Complexity ◽  
Single Error ◽  
On Chip

scholarly journals A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 709
Author(s):  
Abhishek Das ◽  
Nur A. Touba
Keyword(s):  
Optimization Technique ◽  
Error Correcting Code ◽  
Latin Square ◽  
Error Correcting Codes ◽  
Trade Off ◽  
Cache Memories ◽  
Hamming Codes ◽  
Single Error ◽  
Memory Overhead ◽  
On Chip

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.

Precise Cache Profiling for Studying Radiation Effects

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha
Keyword(s):  
Radiation Effects ◽  
Fault Injection ◽  
Error Correcting Codes ◽  
Direct Access ◽  
Transient Faults ◽  
Large Area ◽  
Common Multiple ◽  
Single Event Upsets ◽  
On Chip ◽  
Future Work

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

On-Chip System Level ESD Devices and Clamps

2014 ◽  
pp. 111-198
Author(s):  
Vladislav Vashchenko ◽  
Mirko Scholz
Keyword(s):  
System Level ◽  
On Chip

Systemc and OCAPI-XL Based System-Level Design for Reconfigurable Systems-on-Chip

2006 ◽  
pp. 255-269 ◽  
Author(s):  
Kari Tiensyrjä ◽  
Miroslav Cupak ◽  
Kostas Masselos ◽  
Marko Pettissalo ◽  
Konstantinos Potamianos ◽  
...  
Keyword(s):  
System Level ◽  
Reconfigurable Systems ◽  
System Level Design ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip

Parallel-Pipelined Video Processing in Multicore Heterogeneous Systems on Chip

2021 ◽  
Vol 26 (2) ◽  
pp. 172-183
Author(s):  
E.S. Yanakova ◽  
◽  
G.T. Macharadze ◽  
L.G. Gagarina ◽  
A.A. Shvachko ◽  
...  
Keyword(s):  
Video Processing ◽  
High Efficiency ◽  
Heterogeneous Systems ◽  
Video Data ◽  
System Level ◽  
Video Information ◽  
Systems On Chip ◽  
The Face ◽  
Parallel Pipelined ◽  
On Chip

A turn from homogeneous to heterogeneous architectures permits to achieve the advantages of the efficiency, size, weight and power consumption, which is especially important for the built-in solutions. However, the development of the parallel software for heterogeneous computer systems is rather complex task due to the requirements of high efficiency, easy programming and the process of scaling. In the paper the efficiency of parallel-pipelined processing of video information in multiprocessor heterogeneous systems on a chip (SoC) such as DSP, GPU, ISP, VDP, VPU and others, has been investigated. A typical scheme of parallel-pipelined processing of video data using various accelerators has been presented. The scheme of the parallel-pipelined video data on heterogeneous SoC 1892VM248 has been developed. The methods of efficient parallel-pipelined processing of video data in heterogeneous computers (SoC), consisting of the operating system level, programming technologies level and the application level, have been proposed. A comparative analysis of the most common programming technologies, such as OpenCL, OpenMP, MPI, OpenAMP, has been performed. The analysis has shown that depend-ing on the device finite purpose two programming paradigms should be applied: based on OpenCL technology (for built-in system) and MPI technology (for inter-cell and inter processor interaction). The results obtained of the parallel-pipelined processing within the framework of the face recognition have confirmed the effectiveness of the chosen solutions.

Sign in / Sign up

Export Citation Format

Share Document