On-Chip System Level ESD Devices and Clamps

A turn from homogeneous to heterogeneous architectures permits to achieve the advantages of the efficiency, size, weight and power consumption, which is especially important for the built-in solutions. However, the development of the parallel software for heterogeneous computer systems is rather complex task due to the requirements of high efficiency, easy programming and the process of scaling. In the paper the efficiency of parallel-pipelined processing of video information in multiprocessor heterogeneous systems on a chip (SoC) such as DSP, GPU, ISP, VDP, VPU and others, has been investigated. A typical scheme of parallel-pipelined processing of video data using various accelerators has been presented. The scheme of the parallel-pipelined video data on heterogeneous SoC 1892VM248 has been developed. The methods of efficient parallel-pipelined processing of video data in heterogeneous computers (SoC), consisting of the operating system level, programming technologies level and the application level, have been proposed. A comparative analysis of the most common programming technologies, such as OpenCL, OpenMP, MPI, OpenAMP, has been performed. The analysis has shown that depend-ing on the device finite purpose two programming paradigms should be applied: based on OpenCL technology (for built-in system) and MPI technology (for inter-cell and inter processor interaction). The results obtained of the parallel-pipelined processing within the framework of the face recognition have confirmed the effectiveness of the chosen solutions.

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Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch007 ◽

2014 ◽

pp. 150-179

Author(s):

Haoyuan Ying ◽

Klaus Hofmann ◽

Thomas Hollstein

Keyword(s):

Embedded Systems ◽

Design Optimization ◽

Optimization Methods ◽

Design Methods ◽

System Level ◽

System Level Design ◽

Level Design ◽

On Chip ◽

Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

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Enabling the 2.5D Integration

International Symposium on Microelectronics ◽

10.4071/isom-2012-tp15 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000254-000267 ◽

Cited By ~ 11

Author(s):

John Y. Xie ◽

Hong Shi ◽

Yuan Li ◽

Zhe Li ◽

Arif Rahman ◽

...

Keyword(s):

Thermal Management ◽

Manufacturing Process ◽

System Level ◽

Process Window ◽

Development Effort ◽

Management Options ◽

3D Ic ◽

Industrial Ecosystem ◽

Customer Model ◽

On Chip

3D IC is the viable revolutionary technology that will enable system-level integration, miniaturization, optimal power management, increased data bandwidth, and eventually reduced system cost. Like any breakthrough technologies, it faces many challenges. Design methodology, integration technology, manufacturing process and new industrial ecosystem are the areas of focus. This paper will discuss these challenges and Altera's 3D integration development effort. 2.5D is an intermediate path to true 3D IC using silicon interposer and TSV (Through-Si-Via) stacking. The 2.5D stacking configuration offers different form factor, interconnect path, and thermal management options than monolithic packages, which could help to reduce system level power and thermal management pressure. It offers silicon level interconnect density, low inductive path and wide IO application. However, it's power delivery system (PDN) could be the bottleneck for the system to perform at the intended bandwidth and speed. Thus, the whole system, IC-Interposer-Package-PCB, must be considered holistically, and trade off study and compensation mechanism development are needed in such complex system level integration. There are many different 2.5D integration manufacturing flows currently under development. They can be categorized into two major flow options: Attaching interposer to substrate first, which can be called CoCoS (Chip on Chip on Substrate); or attaching device silicon to interposer first, which is also called CoWoS (Chip on Wafer on Substrate). The major challenges are in the areas of manufacturing process window and yield, thin wafer handling, testability and overall cost of the integration process. ,). This paper will discuss design consideration, manufacturability analysis, Logic/memory devices and silicon interposer interaction, and thermal management to enable the 2.5D integration. System level characterization and correlation with simulations are performed. The challenge of new supply-customer model and industrial ecosystem development associated with 2.5D integration will also be discussed.

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Packaging without the Package - A More Holistic Moore's Law

International Symposium on Microelectronics ◽

10.4071/isom-2017-slide-2 ◽

2017 ◽

Vol 2017 (S1) ◽

pp. 1-40

Author(s):

Subramanian S. Iyer (Subu)

Keyword(s):

System Integration ◽

System Level ◽

Heterogeneous Integration ◽

Power Performance ◽

Wafer Level ◽

Innovative Materials ◽

Barrier To Entry ◽

On Chip ◽

Market Consolidation ◽

Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

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A Comparative Study of Methods for Measurement of Energy of Computing

Energies ◽

10.3390/en12112204 ◽

2019 ◽

Vol 12 (11) ◽

pp. 2204 ◽

Cited By ~ 10

Author(s):

Muhammad Fahad ◽

Arsalan Shahid ◽

Ravi Reddy Manumachu ◽

Alexey Lastovetsky

Keyword(s):

Predictive Models ◽

Ground Truth ◽

System Level ◽

Average Error ◽

Level Energy ◽

Physical Measurements ◽

Wide Range ◽

External Power ◽

On Chip ◽

Multicore Cpus

Energy of computing is a serious environmental concern and mitigating it is an important technological challenge. Accurate measurement of energy consumption during an application execution is key to application-level energy minimization techniques. There are three popular approaches to providing it: (a) System-level physical measurements using external power meters; (b) Measurements using on-chip power sensors and (c) Energy predictive models. In this work, we present a comprehensive study comparing the accuracy of state-of-the-art on-chip power sensors and energy predictive models against system-level physical measurements using external power meters, which we consider to be the ground truth. We show that the average error of the dynamic energy profiles obtained using on-chip power sensors can be as high as 73% and the maximum reaches 300% for two scientific applications, matrix-matrix multiplication and 2D fast Fourier transform for a wide range of problem sizes. The applications are executed on three modern Intel multicore CPUs, two Nvidia GPUs and an Intel Xeon Phi accelerator. The average error of the energy predictive models employing performance monitoring counters (PMCs) as predictor variables can be as high as 32% and the maximum reaches 100% for a diverse set of seventeen benchmarks executed on two Intel multicore CPUs (one Haswell and the other Skylake). We also demonstrate that using inaccurate energy measurements provided by on-chip sensors for dynamic energy optimization can result in significant energy losses up to 84%. We show that, owing to the nature of the deviations of the energy measurements provided by on-chip sensors from the ground truth, calibration can not improve the accuracy of the on-chip sensors to an extent that can allow them to be used in optimization of applications for dynamic energy. Finally, we present the lessons learned, our recommendations for the use of on-chip sensors and energy predictive models and future directions.

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