Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities

2021 ◽  
Author(s):  
Felipe Valencia ◽  
Ilia Polian ◽  
Francesco Regazzoni
Keyword(s):  
Circuit Design ◽  
Design Flow ◽  
Early Assessment ◽  
Fault Attack

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

Design of folded cascode op amp and its application – bandgap reference circuit

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Roohie Kaushik ◽  
Jasdeep Kaur ◽  
Anushree Anushree
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Reference Voltage ◽  
Design Flow ◽  
Slew Rate ◽  
Content Type ◽  
Op Amp ◽  
Complete Study ◽  
Folded Cascode ◽  
Multiplier Circuit

Purpose Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design. Design/methodology/approach This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5. Findings The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill. Research limitations/implications Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out. Practical implications Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools. Social implications BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout. Originality/value FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Development of Superconductor Advanced Integrated Circuit Design Flow using Synopsys Tools

2021 ◽  
pp. 1-1
Author(s):  
Amol Inamdar ◽  
Jushya Ravi ◽  
Sukanya Sagarika Meher ◽  
Stephen Miller ◽  
Mustafa Eren Celik ◽  
...  
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Design Flow ◽  
Integrated Circuit Design

GATE LOCATION CHANGING: AN OPTIMIZATION TECHNIQUE FOR QUANTUM CIRCUITS

2012 ◽  
Vol 10 (03) ◽  
pp. 1250037 ◽  
Author(s):  
NASER MOHAMMADZADEH ◽  
MEHDI SEDIGHI ◽  
MORTEZA SAHEB ZAMANI
Keyword(s):  
Circuit Design ◽  
Optimization Technique ◽  
Quantum Circuit ◽  
Optimization Techniques ◽  
Design Flow ◽  
Quantum Circuits ◽  
Design Constraints ◽  
Gate Location ◽  
Layout Generation ◽  
Critical Paths

During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.

scholarly journals Design of the control system of the laser cleaning robot facing the inner wall of the tiny pipe

2021 ◽  
pp. 55-60
Author(s):  
Ч. Циао
Keyword(s):  
Control System ◽  
Circuit Design ◽  
Power Supply ◽  
Laser Cleaning ◽  
Design Flow ◽  
Single Chip ◽  
Single Chip Microcomputer ◽  
Cleaning Robot ◽  
Chip Technology ◽  
And Control

In order to solve the problem of cleaning small and micro pipelines, the control system of the cleaning robot for small and micro pipelines is designed using single-chip technology. Draw the circuit design flow chart, use PROTEUS software to design the display and control circuit of the DC adjustable regulated power supply, stepping motor. Write and debug the program that controls the start and stop of the motor, accelerate and decelerate, and rotate forward and reverse in keil4; import the program into the single-chip microcomputer, and use the PROTEUS software for simulation and simulation. The experimental results show that the designed control system can realize the two actions of the pipeline robot going straight in the pipeline and the cleaning head rotating.

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