Modeling-based design optimization of wafer-level and chip-scale packaging for RF-MEMS devices

Author(s):  
M. Kelley ◽  
A.P. Malshe ◽  
F. Barlow
Author(s):  
Gil Soo Park ◽  
Ji Hyuk Yu ◽  
Sang Won Seo ◽  
Woo Beom Choi ◽  
Kyeong Kap Paek ◽  
...  

Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.


2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000118-000121
Author(s):  
S. Gropp ◽  
M. Fischer ◽  
A. Frank ◽  
C. Schäffel ◽  
J. Müller ◽  
...  

Abstract The integration of MEMS sensors, microelectronics and RF circuits including RF-MEMS is still a challenging task but becomes crucial for the Internet of Things. A wafer-level silicon-ceramic composite substrate (called SiCer, Silicon-on-Ceramics) allows new options in smart system integration. SiCer substrates combine the benefits of two different worlds of materials. The silicon substrate is a suitable material to build active MEMS devices such as switches and resonators. The ceramic substrate, a Low Temperature Cofired Ceramic (LTCC), is well-known for RF circuit integration including resistors, capacitors and coils. Both materials are co-sintered into a monolithically composite substrate. Chemical and physical modification of the silicon interface allows a low-pressure sintering and therefore new techniques for generating buried cavities at the bond interface. A carbon paste is applied on the LTCC via screen printing. After sintering, this results in a defined cavity. To demonstrate the advantages of the buried cavities within SiCer substrates the fabrication process of a RF-MEMS switch is shown. The switch is intended for a switching matrix to select frequency bands in a mobile LTE receiver. A parallel-plate electrostatic actuation with in-plane movement has been selected. This type of switch allows a large displacement range and a low actuation voltage can be achieved.


Author(s):  
Bangtao Chen ◽  
Vasarla Nagendra Sekhar ◽  
Cheng Jin ◽  
Ying Ying Lim ◽  
Justin See Toh ◽  
...  

Author(s):  
Lei L. Mercado ◽  
Tien-Yu Tom Lee ◽  
Shun-Meen Kuo ◽  
Vern Hause ◽  
Craig Amrine

In discrete RF (Radio Frequency) MEMS (MicroElectroMechanical Systems) packages, MEMS devices were fabricated on Silicon or GaAs (Galium Arsenide) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 Ohm exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis was performed to study the heat dissipation at the switch contact area. The goal is to control the “hot spots” and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials was considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and LTCC (Low-Temperature Cofire Ceramic) were studied. Thermal experiments were conducted to measure the temperature at the contact area and its vicinity as a function of DC and RF powers. Several solutions in material selection and package configurations were explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity.


Author(s):  
John Heck ◽  
Hanan Bar ◽  
Tsung-Kuan A. Chou ◽  
Quan Tran ◽  
Qing Ma ◽  
...  

This paper describes a unique method of encapsulating MEMS switches at the wafer level using a thin-film “microshell” lid and a novel micro-embossing, or “stamping” technique to seal the lid. After fabrication of the MEMS switch and subsequent formation of the microshell, the switches are released through gold tunnels that allow the penetration of a chemical etchant. In a controlled ambient, a “stamp” wafer is aligned to the device wafer, and the wafers are thermally compressed together. This process applies pressure across each tunnel to fuse the gold, thereby sealing the microshell packages. By sealing and passivating the switches at the wafer level, the wafers can be exposed to backend processing, packaging, and assembly steps such as dicing without damaging the sensitive MEMS devices. Furthermore, the size, cost, and complexity of the packaged system are significantly reduced compared to standard wafer bonding processes.


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