Characterization of Light Weight Heat Sink Materials for Thermal Management of Electronics

Thermal management of electronics is a critical part of maintaining high efficiency and reliability. Adequate cooling must be balanced with weight and volumetric requirements, especially for passive air-cooling solutions in electronics applications where space and weight are at a premium. It should be noted that there are systems where thermal solution takes more than 95% of the total weight of the system. Therefore, it is necessary to investigate and utilize advanced materials to design low weight and compact systems. Many of the advanced materials have anisotropic thermal properties and their performances depend strongly on taking advantage of superior properties in the desired directions. Therefore, control of thermal conductivity plays an important role in utilization of such materials for cooling applications. Because of the complexity introduced by anisotropic properties, thermal performances of advanced materials are yet to be fully understood. Present study is an experimental and computational study on characterization of thermal performances of advanced materials for heat sink applications. Numerical simulations and experiments are performed to characterize thermal performances of four different materials. An estimated weight savings in excess of 75% with lightweight materials are observed compared to the traditionally used heat sinks.

A Highly Accelerated Thermal Cycling (HATC) Test for Solder Reliability Assessment in BGA Packages

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

Shape Prediction of Molten Micro-Solder Joints Using Particle Method and Application to Evaluation of Fracture Life

The reliability of a micro-solder joint in a semiconductor structure greatly depends on the solder shape. Therefore, many methods to predict the shape of the molten solder have been proposed [1–3]. However, some problems arise when conventional methods are applied to predict the solder shape of miniaturized and lead-free joints. The first problem is the difficulty in expressing the large deformation and topology change of the solder. In a miniaturized joint, the shape of molten solder changes significantly during the reflow process, and even topology changes (e.g., merging with other solder in a neighboring joint or splitting into several pieces) can occur. These phenomena need to be expressed if we are to predict the solder shape of the miniaturized joint. The second problem is the difficulty in expressing the effect of solder wettability. The solder shape is known to depend on the solder wettability, and the wettability of lead-free solders is different from conventional solders. To predict the lead-free solder shape, we need to express the effect of the wettability. Therefore, I developed a new shape prediction method that solves these problems using the moving-particle semi-implicit (MPS) method [4, 5]. MPS is suitable for calculating incompressible flow and can be used to easily express large deformation and topology changes. However, the original MPS method cannot sufficiently express the effect of solder wettability. Therefore, I enhanced the surface tension formulation of MPS, making it possible to express this effect. I applied this method to predict the solder shapes of various packages (e.g., a thin small outline package (TSOP) and a flip-chip package) and found that the method is effective in predicting the solder shapes of miniaturized joints. Moreover, I was able to evaluate the fracture life of a solder joint with the predicted solder shape by coupling the shape prediction method with our crack propagation analysis method, which was demonstrated at a previous InterPACK [6]. In this crack propagation analysis method, crack initiation points and propagation paths are automatically calculated, and the fracture life is evaluated quantitatively by finite element analysis. I applied these combined methods to evaluate the fracture life of solder joints that had different solder shapes due to different wettability conditions. As a result, I was able to find the differences in crack initiation points and to evaluate crack propagation paths and fracture lives in different wettability conditions.

Analysis of Airflow Distribution Across a Front-to-Rear Server Rack

The most common server racks in data centers are front-to-rear racks, which draw in the cooling air from the front side and discharge it from the backside. In a raised-floor data center the cooling air to these racks is provided by perforated tiles that are placed in front of them. In a high-density data center, these tiles discharge a considerable amount of airflow, which leads to a high-velocity vertical jet in front of the rack. Such a high-velocity jet may bypass the servers located at the bottom of the rack leading to their airflow starvation and potential failure. In this paper the effect of the high-velocity jet on the airflow taken by servers at various heights in the rack is studied. A computer model based on the Computational Fluid Dynamics (CFD) technique is used to predict the airflow distribution through servers stacked in the rack. Two cases are considered. In one case, the rack is placed in the middle of a row of racks in a prefect hot aisle-cold aisle arrangement. The boundary conditions around such a rack is symmetrical. In the other case, the rack is placed in a room with asymmetrical boundary conditions. The characteristics of the servers in the rack are taken from typical 1U and 2U servers manufactured by IBM. It is shown that in general the high-velocity jet has a mild effect on the airflow taken by the servers, and the airflow reduction is limited to servers at the bottom of the rack. Racks in a symmetrical configuration are more susceptible to the airflow starvation. In the most critical conditions, an airflow reduction of 15% is calculated for the server located at the bottom of the rack. Using the result obtained from the computational analysis, a simple model is developed to predict the reduction of the cooling air under the most critical situation for the server placed at the bottom of the rack.

Server-Rack Air Flow and Heat Transfer Interactions in Data Centers

The current study focuses on modeling the server-rack airflow and heat transfer interaction in a data center. In a typical computing facility, the computing requirements are often gradually built-up. For example, in this instance, two servers are placed in a rack designed for a six-server stack. Each server will be separately modeled to the required specifications, and also so that their numbers and placement can be changed. The mass flow rate through the server is determined by examining how pressure profiles develop at the inlet and outlet. This mass flow rate then becomes the input into the rack model. The air inflow temperatures at the front and rear grills were obtained from experiments. The pressure profile into and out of the servers were extracted from the rack model and substituted back into the server model. Iteration continues till an acceptable level of convergence is obtained. To validate the models, experiments were carried out using thermocouples arranged in a 3 × 3 grid on a vertical plane between the exit of the server and the rear cabinet wall of the rack. The results showed that the modeling had captured the essence of the flow and heat transfer interaction. The temperature and pressure profile at the rack inlet and outlet, although in a segmented form, have performed adequately to obtain a good approximation of the flow and temperature distribution within the server/rack. The methodology of passing parameters at the server-rack level using a segmented pressure profile has been established. A similar rack-room level interaction will subsequently be developed. In essence, the methodology is equivalent to replacing the server in the rack and the rack in the room with combined flow network - thermal models. But because of the coupled nature of these two different length scale systems, the models are obtained through an iterative process. The approach enables various combinations of servers and racks to be studied quickly for any undesirable effects of off-design data center operation or layout.

Assessment of 20 Micrometer Diameter Wires for Wire Bond Interconnect Technology

In the domain of wire bonding technology, the size and pitch of bond pads and ball bonds are shrinking to accommodate the demand for higher I/Os and increased functionality per chip area. This trend serves as a catalyst for bonding wire manufacturers to continuously develop lower diameter bonding wires. One mil (25 μm) diameter bonding wire, used widely in this interconnection technique, is now being replaced by 0.8 mil (20 μm) diameter bonding wire. In keeping with the need for higher operating speeds and higher temperatures for today’s ICs, the reliability of ball bonds formed by small diameter wires is of concern and requires investigation. This study explores the effects of 0.8 mil (20 μm) diameter bonding wire on the wire bond ball joint reliability and compares these effects with 1.0 mil (25 μm) diameter bonding wire. The reliability of the ball bonds was assessed using mechanical tests (wire pull and ball shear) for units subjected to stress tests such as the unbiased highly accelerated stress test and high temperature storage tests. The results of this investigation reveal that both the wire diameters are able to sustain their integrity after moisture testing. But, the bond strength degrades after high temperature tests due to the Kirkendall voiding mechanism occurring between gold wire and the aluminum bond pad.

Chip-on-Beam and Hydrostatic Calibration of the Piezoresistive Coefficients on (111) Silicon

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

Quantitative Characterization of Microsystem Dynamics

Development of microelectromechanical system (MEMS) sensors for various applications requires the use of analytical and computational modeling/simulation coupled with rigorous physical measurements. This requirement has led to advancement of an approach that combines computer aided design (CAD) and multiphysics modeling/simulation tools with the state-of-the-art (SOTA) measurement methodology to facilitate reduction of high prototyping costs, long product development cycles, and time-to-market pressures while devising MEMS for a variety of applications. In this approach, a unique, fully integrated software environment for multiscale, multiphysics, high fidelity modeling of MEMS is combined with the optoelectronic laser interferometric microscope methodology for quantitative measurements. The optoelectronic methodology allows remote, noninvasive full-field-of view (FFV) measurements of deformations/motions (under operating conditions) with high spatial resolution, nanometer accuracy, and in near real-time. In this paper, both, the modeling environment (including an analytical process used to quantitatively show the influence that various parameters defining a sensor have on its dynamics — using this process dynamic characteristics of a sensor can be optimized by constraining its nominal dimensions and finding the optimum set of uncertainties in these dimensions that best satisfy design requirements/specifications) and the optoelectronic methodology are described and their applications are illustrated with representative examples demonstrating viability of the approach, combining modeling and measurements, for quantitative characterization of microsystem dynamics. These representative examples demonstrate capability of the approach described herein to quantitatively determine effects of dynamic loads on performance of selected MEMS.

Thermal Management in RF MEMS Ohmic Switches

Today, an ideal microelectromechanical systems (MEMS) switch is no longer a designer’s dream, yet electrothermomechanical (ETM) effects still limit the design possibilities and may adversely affect reliability of microswitches, especially the Ohmic-type cantilever contact switches. The ETM effects are a result of Joule heat generated at the switch contact areas (i.e., electrical interfaces). This heat is due to an electrical signal passing through a microswitch, internal resistance of contact materials, and characteristics of the electrical contact interface. It significantly raises temperature of a microswitch, thus adversely affecting mechanical and electrical properties of the contacts, leading to their wear or even welding, which is a major reliability issue. Fundamental research is being performed to minimize Joule heat effects in the electrical interface area, thus improving the microswitch performance and reliability. Thermal analysis conducted computationally on an Ohmic-type RF MEMS switch indicate heat affected zones (HAZ) and the influence that various parameters have on those zones. Such analysis facilitates mitigation of thermal management issues that may otherwise be detrimental to functional operation of a microswitch.

Pb-Free Process Development for a High End Storage Area Network Application

Lead free solders are being increasingly used in the electronic industry. While most of the electronic products, in terms of volume, are already built lead free, sectors of the industry including high end servers, networking and telecommunications are covered by “lead in solder” exemptions. It is unknown at this point how long these exemptions will last. In addition, many components such as memories have started appearing only in the Pb-free version. As a result, the industry has been pushed to either adopt a mixed assembly process or to transition early to a full Pb-free process. Even though numerous papers have outlined the successful implementation of a Pb-free process, few of them have actually looked at complex high-end multilayer boards in its entirety. This paper focuses on the issues involved in developing an acceptable Pb-free process window for thick, multilayer boards for SMT, Wave soldering, Rework and Press-fit operations. A laminate capable of withstanding Pb-free soldering temperatures was used to construct a 125-mil thick multilayer board with 18 layers which included 8 ground and 10 signal planes. This experiment utilized two popular Pb-free finishes commonly used in the industry: Immersion Silver and high temperature Organic Solderability Preservative (OSP). The widespread SAC 305 alloy with a composition of Sn3.0Ag0.5Cu was used for both SMT and wave soldering. Three sets of assemblies were built: Pb-free, Mixed and Sn/Pb. The mixed assembly mostly used Pb-free components with Sn/Pb solder paste. The impact of increased soldering temperatures on the board, components and reliability of the product were also studied as a part of this research endeavor. Board level reliability tests were conducted by subjecting the boards from 0°C to 100°C Air-to-Air thermal cycling as well as mechanical shock and vibration tests. A suite of reliability and destructive physical analysis (DPA) tests were carried out to establish the quality of the soldering using the eutectic Sn/Pb assembly as the baseline. The study compared the cycling performance of the three sets of assemblies and also looked at the potential impacts of moving to mixed assemblies. Results indicated a reduced process window for Pb-free, especially for the Pb-free wave soldering process due to reduced wetting of the plated through hole barrels as compared to Sn/Pb wave soldering process. The thermal cycling performance of the three sets of assemblies was found to be equivalent after 6000 cycles.