Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

A Hybrid Approach to Investigate Effect of Flip-Chip Packaging on RF MEMS Devices Performance

2008 ◽  
Author(s):  
Li Sun ◽  
Shawn Cunningham ◽  
Art Morris ◽  
Changsoo Jang ◽  
Bongtae Han
Keyword(s):  
Flip Chip ◽  
Rf Mems ◽  
Numerical Models ◽  
Actuation Voltage ◽  
Hybrid Approach ◽  
Optical Measurements ◽  
Mems Devices ◽  
Element Analysis ◽  
Flip Chip Packaging ◽  
Mems Device

A hybrid numerical/experimental scheme to investigate the effect of flip-chip packaging, with and without underfill, on MEMS device performance will be described. Finite element analysis (FEA) is used to model the MEMS assembly and is verified with Twyman/Green (T/G) and Moire´ interferometry, and good agreement between FEA and optical measurements is obtained. The die warpage in assemblies with and without underfill are approximately 0.36 μm and 1.1 μm, respectively. The performance of MEMS devices, fixed-fixed beams, in the packages is characterized by Capacitance-Voltage (C-V) measurement sweeping the actuation voltage yielding the “ON” state and “OFF” state capacitances. Beams in packages without underfill exhibit good actuation behavior while beams in packages with underfill are already in the down-position after packaging. Because die warpage of packages with and without underfill are significantly different, beam anchor relative displacement (BARD), which is affected by the warpage, is used to understand the C-V performance. From numerical models, BARD of packages without underfill is 50 nm and 162 nm for packages with underfill. Compared to a simplified critical BARD calculation (BARDcrit = 57 nm), the large BARD of packages with underfill implies that beams may have buckled, which results in the poor C-V performance. Further modeling of varied die thicknesses and coefficients of thermal expansion (CTE) of the underfill shows that the reduction of BARD is limited because of strong underfill-induced coupling between the die and substrate. It is concluded that the MEMS device and package have to be considered as a coupled design problem to minimize the adverse packaging effect on MEMS devices.

RF-MEMS: Materials and technology, integration and packaging

2003 ◽  
Vol 783 ◽  
Author(s):  
Harrie A. C. Tilmans
Keyword(s):  
Rf Mems ◽  
Mems Devices ◽  
Wafer Level ◽  
Enabling Technology ◽  
High Q ◽  
Tunable Capacitors ◽  
Saw Devices ◽  
Mems Technology ◽  
Layer Thin Film ◽  
New Generation

ABSTRACTMEMS technology is rapidly emerging as an enabling technology to yield a new generation of highperformance RF-MEMS passives, like switches, tunable capacitors, high-Q resonators and tunable filters. This paper presents the progress in RF-MEMS device and package development with focus on relevant technology and material issues. The importance of wafer-level or 0-level packaging of the RF-MEMS devices is elucidated. Examples of 1-level packaging, e.g., chip-on-board or plastic molded 1-level package, are briefly described. The paper concludes in stipulating how integration of RF-MEMS passives with other passives (as inductors, LC filters, SAW devices) and active circuitry (RFICs) can lead to so-called “RF-MEMS system-in-a-package (RF-MEMS-SiP)” modules. The evolution of the RF-MEMS-SiP technology is illustrated using IMEC's microwave multi-layer thin film MCM-D technology.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

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