Effect of Ni(P) thickness of ultrathin ENEPIG on the interfacial reaction and board level reliability of solder joints

2020 ◽  
Author(s):  
Yibo Wang ◽  
Hongfa Pan ◽  
Charles Nan-Cheng Chen ◽  
Ming Li ◽  
Liming Gao
Keyword(s):  
Interfacial Reaction ◽  
Solder Joints ◽  
Reliability Of Solder Joints ◽  
Board Level ◽  
Board Level Reliability

Characterizations of Ball Impact Responses of Tin-Silver-Copper Solder Joints Doped With Nickel or Germanium

2007 ◽  
Author(s):  
Yi-Shao Lai ◽  
Jenn-Ming Song ◽  
Hsiao-Chuan Chang ◽  
Ying-Ta Chiu
Keyword(s):  
High Speed ◽  
Solder Joints ◽  
Ball Impact ◽  
Test Methodology ◽  
Surface Finishes ◽  
Reliability Of Solder Joints ◽  
Tin Silver Copper ◽  
Board Level ◽  
Immersion Tin ◽  
Board Level Reliability

The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted at an impact velocity of 500 mm/s on Sn-4Ag-0.5Cu, Sn-1Ag-0.5Cu, Sn-1Ag-0.5Cu-0.05Ni, Sn-1.2Ag-0.5Cu-0.05Ni, and Sn-1Ag-0.5Cu-0.05Ge package-level solder joints, bonded on substrate pads of immersion tin (IT) and direct solder on pad (DSOP) surface finishes. Differences of BIT results with respect to multi-reflow are also reported.

Board-Level Reliability of Pb-Free Surface Mounted Assemblies during Thermal Shock Testing

2006 ◽  
Vol 15-17 ◽  
pp. 633-638 ◽  
Author(s):  
Jong Woong Kim ◽  
Hyun Suk Chun ◽  
Sang Su Ha ◽  
Jong Hyuck Chae ◽  
Jin Ho Joo ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Solder Joints ◽  
Lead Frame ◽  
Shear Forces ◽  
Microstructural Investigation ◽  
Shock Testing ◽  
Ceramic Capacitor ◽  
Board Level ◽  
Board Level Reliability ◽  
Thermal Shocks

Board-level reliability of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu solder joints was evaluated using thermal shock testing. In the microstructural investigation of the solder joints, the formation of Cu6Sn5 intermetallic compound (IMC) layer was observed between both solders and Cu lead frame, but any crack or newly introduced defect cannot be found even after 2000 cycles of thermal shocks. Shear test of the multi layer ceramic capacitor (MLCC) joints were also conducted to investigate the effect of microstructural variations on the bonding strength of the solder joints. Shear forces of the both solder joints decreased with increasing thermal shock cycles. The reason to the decrease in shear force was discussed with fracture surfaces of the shear tested solder joints.

scholarly journals Effect of Trace Zn Addition on Interfacial Evolution in Sn-10Bi/Cu Solder Joints during Aging Condition

Materials ◽  
2019 ◽  
Vol 12 (24) ◽  
pp. 4240
Author(s):  
Qingfeng Wang ◽  
Hong Chen ◽  
Fengjiang Wang
Keyword(s):  
Interfacial Reaction ◽  
Thermal Aging ◽  
Solder Joints ◽  
Depressing Effect ◽  
Aging Condition ◽  
Obvious Effect ◽  
Cu Substrate ◽  
Zn Addition ◽  
Reliability Of Solder Joints ◽  
Interfacial Evolution

Excessive growth of intermetallic compounds (IMCs) during service affects the reliability of solder joints, so how to suppress the growth of IMC thickness at the interface in solder joints becomes a widespread concern. In this work, the interfacial reaction between Sn-10Bi solder and Cu substrate after thermal aging was investigated. Moreover, to depress the IMC growth at the interface, trace amounts of Zn was added into the Sn-10Bi solder, and the interfacial reactions of Sn-10Bi-xZn solders (x = 0.2, 0.5) and Cu substrate after thermal aging were studied in this paper. Compounds such as Cu6(Sn, Zn)5 and Cu5Zn8 were formed at the interface after adding trace amounts of Zn. The addition of 0.2 and 0.5 wt% Zn significantly inhibited the thickness growth of IMCs and the formation of Cu3Sn IMC at the interface of Sn-10Bi-0.2Zn/Cu and Sn-10Bi-0.5Zn/Cu during thermal aging. Therefore, the addition of trace Zn had an obvious effect on the interfacial reaction of Sn-10Bi/Cu solder joint. Interestingly, the evolution of IMC thickness in Sn-10Bi-0.5Zn/Cu solder joints was completely different from that in Sn-10Bi or Sn-10Bi-0.2Zn solder joints, in which the spalling of IMCs occurred. In order to explore the mechanisms on the depressing effect from the addition of trace Zn, the activation energy Q in solder joints during aging was calculated.

scholarly journals Improvement of Board Level Reliability for μBGA Solder Joints Using Underfill

2003 ◽  
Vol 44 (10) ◽  
pp. 2175-2179 ◽  
Author(s):  
Jong-Min Kim ◽  
Dave F. Farson ◽  
Young-Eui Shin
Keyword(s):  
Solder Joints ◽  
Board Level ◽  
Board Level Reliability

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

2005 ◽  
Vol 28 (2) ◽  
pp. 168-175 ◽  
Author(s):  
Seung Wook Yoon ◽  
Jun Ki Hong ◽  
Hwa Jung Kim ◽  
Kwang Yoo Byun
Keyword(s):  
Solder Joints ◽  
Free Solder ◽  
Board Level ◽  
Board Level Reliability

Design Guideline for Ball Impact Test Apparatus

2006 ◽  
Vol 129 (1) ◽  
pp. 98-104 ◽  
Author(s):  
Chang-Lin Yeh ◽  
Yi-Shao Lai
Keyword(s):  
Impact Test ◽  
Test Apparatus ◽  
Design Guideline ◽  
Ball Impact ◽  
Test Methodology ◽  
Force Profile ◽  
Reliability Of Solder Joints ◽  
Board Level ◽  
Board Level Reliability ◽  
Test Process

The ball impact test is developed as a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. Following classical structural dynamics principles, the ball impact test process is analyzed to provide insights into transient characteristics of this particular test methodology. A design guideline for the ball impact test apparatus based on characteristics of the measured impact force profile is proposed.

Failure Mode and Thermal Performance Analysis of Stacked Panel Level Package (PLP)

2007 ◽  
Author(s):  
Hsiu-Ping Wei ◽  
Ming-Chih Yew ◽  
Chao-Jen Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Failure Mode ◽  
Thermal Performance ◽  
Solder Joints ◽  
Junction Temperature ◽  
Wafer Level ◽  
Element Analysis ◽  
Packaging Technology ◽  
Reliability Of Solder Joints ◽  
Mean Cycle ◽  
Board Level

In this paper, a new packaging technology, chip-on-metal (COM) panel level package (PLP), with stacking and fan-out capabilities is proposed. Moreover, the concept of the COM PLP and the process of its fabrication are described. During the manufacturing process, the trench around the chip is filled with the filler polymer material. Therefore, the solder bumps could be located on both the filler polymer and the chip surfaces by the redistribution lines, and the pitch of the chip side is fanned-out. In our previous research, it was shown that the physical behavior of the COM PLP is different from that of the conventional wafer level package (WLP). To assess the thermal performance and thermo-mechanical characteristic of the proposed PLP, the finite element analysis (FEA) in board level is carried out. The junction temperature and thermal resistance of the COM PLP and the stacked PLP are discussed to study the thermal performance. At the same time, the mean cycle to failure of the solder joints is predicted, and the result shows that the reliability of solder joints can be highly improved by the proposed packaging technology. However, the new failure mode may occur at the metallic traces so the reliability assessment of the signal trace is also investigated. In addition, the parametric analysis of the COM PLP is studied to enhance the thermal performance and reliability characteristic. Thus, the PLP technology will have high potential for various applications in the near future.

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