Technology Trends in 2.5D/3D Packaging and Heterogeneous Integration

2021 ◽  
Author(s):  
Masaya Kawano
Keyword(s):  
Heterogeneous Integration ◽  
3D Packaging ◽  
Technology Trends

INNOVATIVE INTEGRATION BASED ON SILICON-CORE TECHNOLOGIES FOR SENSOR AND COMMUNICATIONS APPLICATIONS

2000 ◽  
Vol 10 (01) ◽  
pp. 205-215 ◽  
Author(s):  
TADAO NAGATSUMA ◽  
KATSUYUKI MACHIDA ◽  
HIROMU ISHII ◽  
NABIL SAHRI ◽  
MITSURU SHINAGAWA ◽  
...  
Keyword(s):  
Low Power ◽  
System Integration ◽  
Lower Cost ◽  
Photonic Devices ◽  
Integration Scheme ◽  
Heterogeneous Integration ◽  
Integration Schemes ◽  
Semiconductor Electronics ◽  
Innovative System ◽  
Technology Trends

This paper describes an innovative system integration scheme wherein heterogeneous materials and devices, including photonic devices as well as electronics, are organically integrated on silicon-core circuitry to achieve better performance, higher functionality and lower cost. First, some general integration technology trends in semiconductor electronics are described. Then, after a discussion of new heterogeneous integration schemes based on silicon-core technologies, recent attempts and applications are shown such as low power LSIs, sensors and micromachine switches on silicon and milimeter-wave photonics.

2.5D / 3D IC Landscape: Market and Technology Trends

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000260-000305
Author(s):  
Andrej Ivankovic ◽  
Thibault Buisson ◽  
Amandine Pizzagalli ◽  
Dave Towne ◽  
Rozalia Beica
Keyword(s):  
Information Exchange ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Image Sensor ◽  
Advanced Technology ◽  
Heterogeneous Integration ◽  
3D Ic ◽  
Continuous Growth ◽  
Major Player ◽  
Technology Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain and continue to be investigated, the spotlight is turning to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D / 3D IC solutions together with upgraded flip chip BGAs aim to revive the cost/performance curve and extend both scaling and functionality roadmaps. Future packages need to tackle the explosion in information exchange translating to high number of I/Os and be able to support heterogeneous integration. This puts particular pressure on die to board interconnects. Technologies to fill the void created in diverging PCB versus IC feature sizes are constantly under development. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect, considered today the most advanced technology, is one emerging option that aims to enable heterogeneous integration. Such a technology is not limited to CMOS scaling in itself, it is rather based on bringing more functionality by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components…) while reducing the package form factor. This functional diversification is also known as More-than-Moore. This work focuses on the analysis of recent developments and future trends of the 2.5D / 3D IC landscape. What's new since last year? TSV technology has already been utilized for several years within the MEMS and CMOS image sensor (CIS) market, but the news is that it finally seems to be happening within the logic and memory domain. Latest products such as AMD Radeon R9 Fury with its 2.5D configuration including HBM stacks and Samsung 3D TSV stacked DRAM, among others, aim for high volume. Fueled by consumer applications such as smartphones and tablets, the MEMS and CIS markets are expected to exhibit continuous growth over the next several years, while in the high-end market, driven by the need for further performance increase, volatile memory and especially DRAM are finally opening the doors of 2.5D / 3D IC commercial adoption. This analysis will cover 2.5D interposer & 3DIC platforms as well as MEMS and CIS TSV packaging. Market forecasts in terms of wafer starts, market revenue, application segments and end-products will be presented. Furthermore, supply chain activities and major player interactions will be analyzed and 3D integration technology roadmaps will be reviewed. In conclusion, this study will aim at providing comprehensive insight into 2.5D / 3D IC market and technology trends.

scholarly journals Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

2019 ◽  
Vol 16 (3) ◽  
pp. 124-135 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Tomonori Ogawa ◽  
Tailong Shi ◽  
Fuhan Liu ◽  
...  
Keyword(s):  
Form Factor ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Large Body ◽  
Electrical Performance ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Glass Panel ◽  
Packaging Technology ◽  
3D Packaging

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

2018 ◽  
Vol 2018 (1) ◽  
pp. 000331-000336 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Tomonori Ogawa ◽  
Tailong Shi ◽  
Fuhan Liu ◽  
...  
Keyword(s):  
Form Factor ◽  
High Performance ◽  
Power Delivery ◽  
Electrical Performance ◽  
Heterogeneous Integration ◽  
Glass Panel ◽  
Process Improvements ◽  
Fundamental Limitations ◽  
Device Integration ◽  
3D Packaging

Abstract This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to <2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.

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