Heterogeneous Integration of Boost Power Supply and On-Chip Solar Cell using triple well CMOS Process

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

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Potential of a power supply on chip for solar cell based energy harvesting systems

2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS) ◽

10.1109/peds.2017.8289175 ◽

2017 ◽

Author(s):

Kosei Yamada ◽

Kengo Hiura ◽

Satoshi Matsumoto

Keyword(s):

Solar Cell ◽

Energy Harvesting ◽

Power Supply ◽

Harvesting Systems ◽

On Chip

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Research on Efficiency of Solar Cell Integrated with Energy Management Circuitry on Chip

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.667.396 ◽

2014 ◽

Vol 667 ◽

pp. 396-400

Author(s):

Li Xian Xiao ◽

Yong Tai He ◽

Jin Hao Liu ◽

Yue Hong Peng

Keyword(s):

Solar Cells ◽

Solar Cell ◽

Energy Management ◽

Conversion Efficiency ◽

Power Supply ◽

Back Surface ◽

Simulation Tools ◽

Surface Field ◽

Micro Power ◽

On Chip

In photoelectric micro-power supply integrated on chip, the conversion efficiency of solar cell was lower compared with canonical solar cell. In order to improve the conversion efficiency of the solar cell, three technologies (fabricating back surface field, fabricating surfaces texture and reflector) were adopted in integrated process of photoelectric micro-power supply on chip. The relevant theory of the three technologies was introduced. The optimum schedule of the photoelectric micro-power supply integrated on SOI wafer was proposed. The conversion efficiency of solar cells was analyzed by simulation tools (PC1D). The results prove the conversion efficiency of solar cells was improved from 9. 34% to 13.3%.

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A Power Supply On-Chip with Low Power Dissipation for Low Power Digital Integrated Circuit Applications

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.513-517.3844 ◽

2014 ◽

Vol 513-517 ◽

pp. 3844-3849

Author(s):

Hai Peng Zhang ◽

Shao Dan Yang ◽

Ya Dong Yin ◽

De Jun Wang

Keyword(s):

Low Power ◽

Power Supply ◽

Integrated Circuit ◽

Power Dissipation ◽

Cmos Process ◽

Low Power Dissipation ◽

Standby Power ◽

Quiescent Current ◽

On Chip ◽

Digital Integrated Circuit

An implementation method of a power supply on-chip (PSOC) was presented for low power digital integrated circuit (IC) applications in this paper. The PSOC consists of a main power supply and a backup low power dissipation power supply, which is featured of micro-standby power consumption and fast switching. The PSOC was designed according to the design rules of SMIC 0.18μm CMOS process and validated both through simulation and silicon verification. The active area is about 0.035mm2 in fact. Post-layout simulation results indicate that output voltage of the PSOC is regulable in the range of 1.52~2.5V as input voltage is in the range of 2.0~3.6V, in which output of the main power supply is regulable in the range of 1.75~ 1.84V. The maximum quiescent current of main power supply is 16.23μA, while the maximum quiescent current of standby power is only 0.552μA. Experimental results indicate that the PSOC is capable of providing energy for the system digital IC implementation. Its power switching time is less than 148μs at the load capacitance of CL =56nF.

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Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.543.176 ◽

2013 ◽

Vol 543 ◽

pp. 176-179 ◽

Cited By ~ 1

Author(s):

D.Q. Zhao ◽

Xia Zhang ◽

P. Liu ◽

F. Yang ◽

C. Lin ◽

...

Keyword(s):

Silicon Nitride ◽

Hole Mobility ◽

Micro Electro Mechanical System ◽

Cmos Process ◽

Standard Cmos Process ◽

Ir Sensor ◽

Cantilever Structure ◽

Cmos Mems ◽

On Chip ◽

Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

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A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽

10.3390/electronics10010068 ◽

2021 ◽

Vol 10 (1) ◽

pp. 68

Author(s):

Woorham Bae ◽

Sung-Yong Cho ◽

Deog-Kyoon Jeong

Keyword(s):

Finite Impulse Response ◽

Cmos Process ◽

Pci Express ◽

Fully Integrated ◽

Peripheral Component Interconnect ◽

Low Power Cmos ◽

On Chip ◽

Output Driver ◽

Wide Operating ◽

28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

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Design and Implementation of a 12-Bit 100MS/s ADC

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.229-231.1507 ◽

2012 ◽

Vol 229-231 ◽

pp. 1507-1510

Author(s):

Xiang Ning Fan ◽

Hao Zheng ◽

Yu Tao Sun ◽

Xiang Yan

Keyword(s):

Power Consumption ◽

Power Supply ◽

Stage Structure ◽

Digital Calibration ◽

Cmos Process ◽

Pipelined Adc ◽

Dynamic Comparator ◽

Flash Adc ◽

Design And Implementation ◽

Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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