Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

Abstract This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to <2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.

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Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.930748 ◽

2019 ◽

Vol 16 (3) ◽

pp. 124-135 ◽

Cited By ~ 5

Author(s):

Siddharth Ravichandran ◽

Shuhei Yamada ◽

Tomonori Ogawa ◽

Tailong Shi ◽

Fuhan Liu ◽

...

Keyword(s):

Form Factor ◽

High Performance ◽

Coefficient Of Thermal Expansion ◽

Large Body ◽

Electrical Performance ◽

Heterogeneous Integration ◽

Wafer Level ◽

Glass Panel ◽

Packaging Technology ◽

3D Packaging

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

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Low-Cost Non-TSV Based 3D Packaging Using Glass Panel Embedding (GPE) for Power-Efficient, High-Bandwidth Heterogeneous Integration

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2019.00277 ◽

2019 ◽

Author(s):

Siddharth Ravichandran ◽

Shuhei Yamada ◽

Fuhan Liu ◽

Vanessa Smet ◽

Mohanalingam Kathaperumal ◽

...

Keyword(s):

Low Cost ◽

Heterogeneous Integration ◽

Glass Panel ◽

Power Efficient ◽

3D Packaging ◽

High Bandwidth

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Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2017dpc-tp2_presentation5 ◽

2017 ◽

Vol 2017 (DPC) ◽

pp. 1-20

Author(s):

Seung Wook Yoon

Keyword(s):

Form Factor ◽

Power Efficiency ◽

High Performance ◽

Electrical Characterization ◽

Cost Effective ◽

Electrical Performance ◽

Wearable Electronics ◽

Wafer Level ◽

Low Profile ◽

Line Spacing

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

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3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

2019 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm19573.2019.8993583 ◽

2019 ◽

Author(s):

Han Wui Then ◽

C. Y. Huang ◽

B. Krist ◽

K. Jun ◽

K. Lin ◽

...

Keyword(s):

Energy Efficient ◽

High Performance ◽

Power Delivery ◽

High Resistivity ◽

Heterogeneous Integration ◽

Si Substrate ◽

Metal Gate ◽

High K

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3D Integrated Packaging Approach for High Performance Processor-Memory Module

International Symposium on Microelectronics ◽

10.4071/isom-2013-wa15 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000452-000457 ◽

Cited By ~ 1

Author(s):

S. C. Polzer ◽

W. L. Wilkins ◽

J. L. Fasig ◽

M. J. Degerstrom ◽

B. K. Gilbert ◽

...

Keyword(s):

Thermal Management ◽

High Performance ◽

Mechanical Design ◽

Power Delivery ◽

Memory Module ◽

Thermal Test ◽

Power Delivery Network ◽

3D Packaging ◽

Test Chips ◽

Delivery Network

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling—are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

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Technology Trends in 2.5D/3D Packaging and Heterogeneous Integration

2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) ◽

10.1109/edtm50988.2021.9421033 ◽

2021 ◽

Author(s):

Masaya Kawano

Keyword(s):

Heterogeneous Integration ◽

3D Packaging ◽

Technology Trends

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Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

NPG Asia Materials ◽

10.1038/s41427-021-00314-y ◽

2021 ◽

Vol 13 (1) ◽

Author(s):

Muhammad Naqi ◽

Kyung Hwan Choi ◽

Hocheon Yoo ◽

Sudong Chae ◽

Bum Jun Kim ◽

...

Keyword(s):

Low Temperature ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Optical Measurements ◽

Electrical Performance ◽

Large Area ◽

Nanowire Network ◽

P Type ◽

Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

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Recent Advances in ZnO-Based Carbon Monoxide Sensors: Role of Doping

Sensors ◽

10.3390/s21134425 ◽

2021 ◽

Vol 21 (13) ◽

pp. 4425

Author(s):

Ana María Pineda-Reyes ◽

María R. Herrera-Rivera ◽

Hugo Rojas-Chávez ◽

Heriberto Cruz-Martínez ◽

Dora I. Medina

Keyword(s):

Carbon Monoxide ◽

High Performance ◽

Gas Sensing ◽

Experimental Studies ◽

Electrical Performance ◽

Long Term Stability ◽

Sensing Applications ◽

Recent Advances ◽

Sensitivity And Selectivity ◽

Doped Zno

Monitoring and detecting carbon monoxide (CO) are critical because this gas is toxic and harmful to the ecosystem. In this respect, designing high-performance gas sensors for CO detection is necessary. Zinc oxide-based materials are promising for use as CO sensors, owing to their good sensing response, electrical performance, cost-effectiveness, long-term stability, low power consumption, ease of manufacturing, chemical stability, and non-toxicity. Nevertheless, further progress in gas sensing requires improving the selectivity and sensitivity, and lowering the operating temperature. Recently, different strategies have been implemented to improve the sensitivity and selectivity of ZnO to CO, highlighting the doping of ZnO. Many studies concluded that doped ZnO demonstrates better sensing properties than those of undoped ZnO in detecting CO. Therefore, in this review, we analyze and discuss, in detail, the recent advances in doped ZnO for CO sensing applications. First, experimental studies on ZnO doped with transition metals, boron group elements, and alkaline earth metals as CO sensors are comprehensively reviewed. We then focused on analyzing theoretical and combined experimental–theoretical studies. Finally, we present the conclusions and some perspectives for future investigations in the context of advancements in CO sensing using doped ZnO, which include room-temperature gas sensing.

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