Cu-Cu Thermocompression Bonding with Cu-Nanowire Films for Power Semiconductor Die-Attach on DBC Substrates

Author(s):  
Zechun Yu ◽  
Ying Zhao Tan ◽  
Christoph F. Bayer ◽  
Hubert Rauh ◽  
Andreas Schletz ◽  
...  
2019 ◽  
Vol 2019 (1) ◽  
pp. 000312-000315
Author(s):  
Maciej Patelka ◽  
Sho Ikeda ◽  
Koji Sasaki ◽  
Hiroki Myodo ◽  
Nortisuka Mizumura

Abstract High power semiconductor applications require a Thermal Interface Die Attach Material with high thermal conductivity to efficiently release the heat generated from these devices. Current Thermal Interface Material solutions such as thermal grease, thermal pads and silicones have been industry standards, however may fall short in performance for high temperature or high-power applications. This presentation will focus on development of a cutting-edge Die Attach Solution for Thermal Interface Management, focusing on Fusion Type epoxy-based Ag adhesive with an extremally low Storage Modulus and the Thermal Conductivity reaching up to 30W/mK, and also Very Low Modulus, Low-Temperature Pressureless Sintered Silver Die Attach with the Thermal Conductivity of 70W/mK.


2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000099-000102
Author(s):  
Bernard Leavitt ◽  
Andy C. Mackie

Abstract The need for high-temperature solders is growing as RF and power semiconductor devices continue to get smaller, with power density increasing both as a consequence of the shrink and as a result of increased power ratings. AuSn20 eutectic solder (Indalloy®182) has been the workhorse for high-temperature, high-reliability, small die-attach applications for many years; however, as junction temperatures (Tj) increase, the gold-tin eutectic is beginning to reach its limit of utility. Higher temperatures cause increased thermal fatigue, and even delamination is seen at the solder joints. The next option for RF and power semiconductor manufacturers needing these higher temperatures is either AuGe12 (Indalloy®183) or AuSi3.2 (Indalloy®184) eutectic alloy (see Table I).Table 1.Key properties of Au-based eutectic alloys. Over the years, many customers have tried AuGe12 and the feedback has been that the alloy has poor solderability, which manifests as large voids in the bond. Voids are poor conductors of heat, which create hot spots, and are the primary cause of premature failures.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000136-000141 ◽  
Author(s):  
Amanda Hartnett ◽  
Seth Homer ◽  
Donald Beck ◽  
Daniel Evans

High-power semiconductor devices, such as high-brightness Light Emitting Diodes (LEDs), must be mounted using a robust adhesive material to handle the temperature fluctuations generated by the chip and the mechanical stresses due to the coefficient of thermal expansion (CTE) mismatches between the die material and substrate it is mounted to. The selected material must also comply with current legislation restricting manufactured products containing numerous materials including some that were historically popular in HB LED applications due to environmental concerns. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented in this paper. Utilizing a Palomar Technologies die bonder, AuSn solder preforms and paste will be placed/dispensed and reflowed using a Pulsed Heat System (PHS). Evaluation methods comparing these means of eutectic die attach to a pre-plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test methods as well as hypotheses of results.


Author(s):  
L. Smith ◽  
T.S. Kalkur

Abstract There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. Vbe, Vgs) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.


2013 ◽  
Vol 393 ◽  
pp. 57-62
Author(s):  
Vemal Raja Manikam ◽  
Kim Seah Tan ◽  
Khairunisak Abdul Razak ◽  
Kuan Yew Cheong

A die attach nanopaste for high temperature use on silicon carbide (SiC) based power semiconductor devices was developed utilizing silver (Ag) and aluminium (Al) nanoparticles as well as organic additives. Total nanoparticle content was varied at 84.7, 85.5, 86.2 and 87 wt%, while the Ag to Al ratio was fixed to 80:20. The die attach nanopaste was sintered in open air at 380 °C for 30 minutes to create an Ag-Al inter-metallic compound between the SiC die and substrate. To determine the mechanical attributes of the post-sintered die attach interlayer, nanoindentation was performed on the samples. It was found that, a low Young modulus of elasticity, E, between 9.3-9.8 GPa was obtained. This was followed by a reduction in hardness as well as stiffness for the post-sintered Ag80-Al20 die attach material when compared against that of solder alloys or bulk metals. The formation of pores in the die attach material as it underwent sintering is believed to have contributed to this decrease in mechanical properties. The findings of this research enables the possibility of introducing a much cheaper die attach material for high temperature devices, which also has excellent mechanical properties to alleviate thermal mismatch issues between the semiconductor die and substrate.


2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000200-000207 ◽  
Author(s):  
Dean Hamilton ◽  
Liam Mills ◽  
Steve Riches ◽  
Philip Mawby

The recent commercial availability of silicon carbide power semiconductor devices are theoretically capable of operating at temperatures well beyond the limits of silicon devices and have generated an interest in developing high temperature capable packaging solutions to match. In this work, the performance and reliability of a number of commercially available silicon carbide power MOSFET dies from multiple vendors was determined for die temperatures up to 350°C. Although these results have demonstrated a number of aging effects and very high on-state resistances at high temperatures, it appears that these devices can perform reliably even in air atmospheres for 100 hours or more at 350°C. In addition, commercially available DBC type ceramic-based substrates have been evaluated for their thermal cycling performance and candidate high temperature capable die attach materials including silver sinter paste and tin and gold-tin pre-form based transient liquid phase types have also been evaluated. These results have demonstrated that the active metal brazed substrates, both copper and aluminium variants, in conjunction with the silicon carbide dies and silver sinter die attach may serve as the basis for high temperature power modules, and may be operated reliably in thermal cycled applications and in air atmospheres up to 300°C. Due to large threshold voltage shift of the SiC MOSFETs at these temperatures, it may be necessary to implement a negative gate bias capability. This work has been carried out under the Innovate UK supported project HITEC, led by Prodrive and also including The University of Warwick, GE Aviation Systems, Ricardo, TT Electronics Semelab, Diamond Hard Surfaces and GaN Systems.


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