Fabrication Process Flow of Antenna-in-Package Fan-out Wafer Level Packaging

Author(s):  
Lau Boon Long ◽  
David Ho ◽  
Lim Teck Guan ◽  
Hsiao Hsiang Yao ◽  
Lim Pei Siang ◽  
...  
2010 ◽  
Vol 7 (3) ◽  
pp. 125-130
Author(s):  
Deniz S. Tezcan ◽  
Bivragh Majeed ◽  
Yann Civale ◽  
Philippe Soussan ◽  
Eric Beyne

Imec is developing two TSV flavors for Si thicknesses of 50 and 100 μm for various wafer level packaging (WLP) applications where thin dice are stacked and electrically connected to each other through post CMOS processed TSVs and microbumps. As a differentiator, these TSV technologies use spin-on dielectric polymers as the insulating liner. A three-mask process sequence is implemented for fabrication of both TSV types; however, the TSV shape, the process flow, and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for post CMOS compatibility. For both TSV types, electrically yielding TSV connected daisy chains are measured on the fabricated wafers and the reliability of the TSVs while undergoing thermal cycle tests is analyzed.


2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka

Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.


Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2605
Author(s):  
Ashley Novais ◽  
Carlos Calaza ◽  
José Fernandes ◽  
Helder Fonseca ◽  
Patricia Monteiro ◽  
...  

Multisite neural probes are a fundamental tool to study brain function. Hybrid silicon/polymer neural probes combine rigid silicon and flexible polymer parts into one single device and allow, for example, the precise integration of complex probe geometries, such as multishank designs, with flexible biocompatible cabling. Despite these advantages and benefiting from highly reproducible fabrication methods on both silicon and polymer substrates, they have not been widely available. This paper presents the development, fabrication, characterization, and in vivo electrophysiological assessment of a hybrid multisite multishank silicon probe with a monolithically integrated polyimide flexible interconnect cable. The fabrication process was optimized at wafer level, and several neural probes with 64 gold electrode sites equally distributed along 8 shanks with an integrated 8 µm thick highly flexible polyimide interconnect cable were produced. The monolithic integration of the polyimide cable in the same fabrication process removed the necessity of the postfabrication bonding of the cable to the probe. This is the highest electrode site density and thinnest flexible cable ever reported for a hybrid silicon/polymer probe. Additionally, to avoid the time-consuming bonding of the probe to definitive packaging, the flexible cable was designed to terminate in a connector pad that can mate with commercial zero-insertion force (ZIF) connectors for electronics interfacing. This allows great experimental flexibility because interchangeable packaging can be used according to experimental demands. High-density distributed in vivo electrophysiological recordings were obtained from the hybrid neural probes with low intrinsic noise and high signal-to-noise ratio (SNR).


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