Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology

An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover, the detection results can be written in the in-pixel storage node for days, enabling off-line and non-destructive reading. The high spatial resolution micro-detectors can be used to extract the actual parameters of the incident EUV on wafers, including light intensity, exposure time and energy, key to optimization of lithographic processes in 5 nm FinFET technology and beyond.

Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

Optoelectronic mixing with high-frequency graphene transistors

Graphene is ideally suited for optoelectronics. It offers absorption at telecom wavelengths, high-frequency operation and CMOS-compatibility. We show how high speed optoelectronic mixing can be achieved with high frequency (~20 GHz bandwidth) graphene field effect transistors (GFETs). These devices mix an electrical signal injected into the GFET gate and a modulated optical signal onto a single layer graphene (SLG) channel. The photodetection mechanism and the resulting photocurrent sign depend on the SLG Fermi level (EF). At low EF (<130 meV), a positive photocurrent is generated, while at large EF (>130 meV), a negative photobolometric current appears. This allows our devices to operate up to at least 67 GHz. Our results pave the way for GFETs optoelectronic mixers for mm-wave applications, such as telecommunications and radio/light detection and ranging (RADAR/LIDARs.)

Si and SiGe Nanowire for Micro-Thermoelectric Generator: A Review of the Current State of the Art

In our environment, the large availability of wasted heat has motivated the search for methods to harvest heat. As a reliable way to supply energy, SiGe has been used for thermoelectric generators (TEGs) in space missions for decades. Recently, micro-thermoelectric generators (μTEG) have been shown to be a promising way to supply energy for the Internet of Things (IoT) by using daily waste heat. Combining the predominant CMOS compatibility with high electric conductivity and low thermal conductivity performance, Si nanowire and SiGe nanowire have been a candidate for μTEG. This review gives a comprehensive introduction of the Si, SiGe nanowires, and their possibility for μTEG. The basic thermoelectric principles, materials, structures, fabrication, measurements, and applications are discussed in depth.

Memristors: Understanding, Utilization and Upgradation for Neuromorphic Computing

The next generation of artificial intelligence systems is generally governed by a new electronic element called memristor. Memristor-based computational system is responsible for confronting memory wall issues in conventional system architecture in the big data era. Complementary Metal Oxide Semiconductor (CMOS) compatibility, nonvolatility and scalability are the important properties of memristor for designing such computing architecture. However, some of the concerns, such as analogue switching and stochasticity, need to be addressed for the use of memristor in novel architecture. Here, we reviewed a number of important scientific works on memristor materials, electrical performance and their integration. In addition, strategies to address the challenges of memristor integration in neuromorphic computing are also being investigated.

Oxygen vacancy control as a strategy to achieve highly reliable hafnia ferroelectrics using oxide electrode

Recently, hafnia ferroelectrics with two spontaneous polarization states have attracted marked attention for non-volatile, super-steep switching devices, and neuromorphic application due to their fast switching, scalability, and CMOS compatibility.

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.