Quantum short-channel compact modeling of drain-current in double-gate MOSFET

2005 ◽  
Author(s):  
D. Munteanu ◽  
J.-L. Autran ◽  
X. Loussier ◽  
S. Harrison ◽  
R. Cerutti ◽  
...  
Keyword(s):  
Drain Current ◽  
Compact Modeling ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet

Quantum Short-channel Compact Modelling of Drain-Current in Double-Gate MOSFET

2006 ◽  
Vol 50 (4) ◽  
pp. 680-686 ◽  
Author(s):  
Daniela Munteanu ◽  
Jean-Luc Autran ◽  
Xavier Loussier ◽  
Samuel Harrison ◽  
Robin Cerutti ◽  
...  
Keyword(s):  
Drain Current ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet

Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs

2017 ◽  
Vol 16 (2) ◽  
pp. 347-354 ◽  
Author(s):  
Chandan Yadav ◽  
Mayank Agrawal ◽  
Amit Agarwal ◽  
Yogesh Singh Chauhan
Keyword(s):  
Drain Current ◽  
Compact Modeling ◽  
Double Gate ◽  
Charge Capacitance

scholarly journals Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019 ◽  
Vol 8 (2S6) ◽  
pp. 783-791
Keyword(s):  
Field Effect Transistors ◽  
Scaling Limit ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Length Variation ◽  
Gate Length ◽  
Double Gate ◽  
Simulation Design ◽  
Short Channel ◽  
Fully Depleted

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

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