Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs

2017 ◽  
Vol 16 (2) ◽  
pp. 347-354 ◽  
Author(s):  
Chandan Yadav ◽  
Mayank Agrawal ◽  
Amit Agarwal ◽  
Yogesh Singh Chauhan
2014 ◽  
Vol 492 ◽  
pp. 306-310
Author(s):  
Billel Smaani ◽  
Mourad Bella ◽  
Saϊda Latreche

In this paper, a compact modeling of lightly doped nanoscale Double Gate (DG) MOSFET transistor is presented. In the first time, a DG MOSFET transistor with long channel is considered. In this case, by using 1-D Poissons equation and applying the Gauss law at the interface of Silicone/Oxide, the static behavior of the long channel DG MOSFET can be observed by simple relationships between charges-voltages and charges-drain current. In second time, the dynamic behavior of the device is described through the intrinsic trans-capacitances. The present results (obtained using MATLAB) are validated by comparing them with those obtained using commercial software (Silvaco Atlas-TCAD).


2010 ◽  
Vol 41 (10) ◽  
pp. 688-692 ◽  
Author(s):  
Wei Wang ◽  
Huaxin Lu ◽  
Jooyoung Song ◽  
Shih-Hsien Lo ◽  
Yuan Taur

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