The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance

Author(s):  
N.R. Mohapatra ◽  
M.P. Desai ◽  
S.G. Narendra ◽  
V. Ramgopal Rao
2001 ◽  
Vol 41 (7) ◽  
pp. 1045-1048 ◽  
Author(s):  
N.R. Mohapatra ◽  
A. Dutta ◽  
G. Sridhar ◽  
M.P. Desai ◽  
V.R. Rao

2002 ◽  
Vol 49 (5) ◽  
pp. 826-831 ◽  
Author(s):  
N.R. Mohapatra ◽  
M.P. Desai ◽  
S.G. Narendra ◽  
V.R. Rao

2005 ◽  
Vol 103-104 ◽  
pp. 3-6 ◽  
Author(s):  
Alessio Beverina ◽  
M.M. Frank ◽  
H. Shang ◽  
S. Rivillon ◽  
F. Amy ◽  
...  

We review the impact of semiconductor surface preparation on the performance of metal-oxidesemiconductor field-effect transistor (MOSFET) gate stacks. We discuss high-permittivity dielectrics such as hafnium oxide and aluminum oxide on silicon and on the high carrier mobility substrate germanium. On Si, scaling of the gate stack is the prime concern. On Ge, fundamental issues of chemical and electrical passivation need to be resolved. Surface treatments considered include oxidation, nitridation, hydrogenation, chlorination, and organic functionalization.


Author(s):  
L. Manchanda ◽  
B. Busch ◽  
M.L. Green ◽  
M. Morris ◽  
R.B. van Dover ◽  
...  
Keyword(s):  

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.


Sign in / Sign up

Export Citation Format

Share Document