Radiation hardened 2Mbit SRAM in 180nm CMOS technology

Author(s):  
A. Arbat ◽  
C. Calligaro ◽  
Y. Roizin ◽  
D. Nahmad
2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000046-000050
Author(s):  
R. Bannatyne ◽  
D. Gifford ◽  
K. Klein ◽  
C. Merritt

Abstract VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.


2018 ◽  
Vol 170 ◽  
pp. 01021
Author(s):  
Jeffrey Prinzie ◽  
Jorgen Christiansen ◽  
Paulo Moreira ◽  
Michiel Steyaert ◽  
Paul Leroux

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.


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