High temperature / radiation hardened capable ARM® Cortex®-M0 microcontrollers

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000046-000050
Author(s):  
R. Bannatyne ◽  
D. Gifford ◽  
K. Klein ◽  
C. Merritt
Keyword(s):  
High Temperature ◽  
Lower Cost ◽  
Cmos Technology ◽  
The Other ◽  
Device Performance ◽  
High Radiation ◽  
Plastic Package ◽  
Radiation Hardened ◽  
Temperature Radiation ◽  
On Chip

Abstract VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.

scholarly journals On modeling the problems of high-temperature radiation gas dynamics

1984 ◽  
pp. 1-17
Author(s):  
Vladimir Yakovlevich Gol’din ◽  
Dinamika Alekseevna Gol'dina ◽  
Andrey Vasilievich Kolpakov ◽  
Alexander Victorovich Shilkov
Keyword(s):  
High Temperature ◽  
Energy Density ◽  
Numerical Methods ◽  
Mathematical Models ◽  
Gas Dynamics ◽  
Radiation Energy ◽  
High Radiation ◽  
Radiation Energy Density ◽  
Temperature Radiation ◽  
Radiation Gas Dynamics

Mathematical models of High-Temperature Radiation Gas Dynamics (HTRGD) are considered. The possibility of instability of contact boundaries at a high radiation energy density is shown. Equations of the three-temperature approximation are consistently derived. Numerical methods for solving the problems of HTRGD are discussed.

Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000020-000026 ◽  
Author(s):  
Rex Lowther ◽  
David Gifford ◽  
Wesley Morris ◽  
Jim Jensen ◽  
Scott Peterson ◽  
...  
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Cmos Technology ◽  
Radiation Environment ◽  
Cmos Process ◽  
Bulk Silicon ◽  
Process Technology ◽  
On Chip ◽  
Silicon Cmos ◽  
Integration Levels

Silicon Space Technology has developed a commercial bulk CMOS process technology, HardSIL™, which allows optimization of performance, power, and lifetime at high temperatures. A method for preventing latchup, originally developed for use in the space radiation environment, is presently applied to terrestrial high-temperature environments. With the possibility of latchup eliminated in scaled CMOS technology nodes, further designs specific for high-temperature environments have proceeded well. This novel technology has been applied to our 18Mb synchronous burst SBRAM and our ARM® Cortex® M0 microcontroller, and in two CMOS processes at the 130nm technology node (Texas Instruments and GLOBALFOUNDRIES). Extensive temperature testing on these parts demonstrates that bulk silicon CMOS technology has a practical temperature limit of 250°C or higher. Both the microcontroller and the SBRAM have been tested with clock rates up to 70MHz and at temperatures up to 260°C. Both parts have performed without error and without latchup under these conditions, and with low operating current and low leakage current. For example, the 130 million-transistor 18Mb SBRAM has average core leakage current of 580mA at 250°C and core voltage of 1.5V with test lots and simulations showing further reduction in leakage in the next, terrestrial version of this part. In addition, the 18Mb SBRAM is undergoing an endurance test at 250°C, presently at the 2500 hour milestone. Operation at temperatures beyond the present limit of the testing equipment (260°C) appears possible from extrapolation of current data. Integration levels of greater than 8 million gates on a bulk CMOS device would allow multi-core processors with large on-chip secondary caches. Additional DSP engines or other compute engines can be accommodated for processing high resolution three dimensional images in real time. This would provide substantial distributed processing in drilling or jet engine control. These system-on-chip (SOC) integration levels can substantially reduce mechanical failures in a subsystem by reducing the number of wire bonds from greater than 1000 connections to less than 100 connections. Integration of mixed-signal A/Ds and D/As as well as on-chip power management provides a path to further reduction in mechanical connections in a sub-system.

LOW-POWER INSTRUCTION ADDRESS BUS CODING WITH XOR–BITS ARCHITECTURE

2009 ◽  
Vol 18 (01) ◽  
pp. 45-57 ◽  
Author(s):  
CHIH-PENG FAN ◽  
CHIA-HAO FANG
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Cmos Technology ◽  
Experimental Results ◽  
The Other ◽  
Total Power ◽  
Delay Faults ◽  
Coding Method ◽  
On Chip ◽  
Exclusive Or

In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology.

High-Temperature Operation of Photonic-Crystal Lasers for On-Chip Optical Interconnection

2012 ◽  
Vol E95.C (7) ◽  
pp. 1244-1251 ◽  
Author(s):  
Koji TAKEDA ◽  
Tomonari SATO ◽  
Takaaki KAKITSUKA ◽  
Akihiko SHINYA ◽  
Kengo NOZAKI ◽  
...  
Keyword(s):  
High Temperature ◽  
Photonic Crystal ◽  
Optical Interconnection ◽  
On Chip ◽  
High Temperature Operation

CLC 18.10LN

Alloy Digest ◽  
2006 ◽  
Vol 55 (1) ◽  
Keyword(s):  
Stainless Steel ◽  
Corrosion Resistance ◽  
Shear Strength ◽  
High Temperature ◽  
Austenitic Stainless Steel ◽  
Stainless Steels ◽  
The Other ◽  
Low Carbon ◽  
Good Corrosion Resistance ◽  
Temperature Performance

Abstract CLC 18.10LN is an austenitic stainless steel with 18% Cr, 9.5% Ni, and 0.14% N to provide good corrosion resistance at strengths above the other low-carbon stainless steels. This datasheet provides information on composition, physical properties, elasticity, tensile properties, and shear strength as well as creep. It also includes information on high temperature performance and corrosion resistance as well as forming, machining, and joining. Filing Code: SS-950. Producer or source: Industeel USA, LLC.

Investigation of Die Tilting of Packages with Single and Multi-chips

2018 ◽  
Author(s):  
Lo Chea Wee ◽  
Tan Sze Yee ◽  
Gan Sue Yin ◽  
Goh Cin Sheng
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Electron Beam ◽  
Optical Microscopy ◽  
Device Performance ◽  
Electronic Components ◽  
Area Of Interest ◽  
On Chip ◽  
Scanning Electron

Abstract Advanced package technology often includes multi-chips in one package to accommodate the technology demand on size & functionality. Die tilting leads to poor device performance for all kinds of multi-chip packages such as chip by chip (CbC), chip on chip (CoC), and the package with both CbC and CoC. Traditional die tilting measured by optical microscopy and scanning electron microscopy has capability issue due to wave or electron beam blocking at area of interest by electronic components nearby. In this paper, the feasibility of using profilemeter to investigate die tilting in single and multi-chips is demonstrated. Our results validate that the profilemeter is the most profound metrology for die tilting analysis especially on multi-chip packages, and can achieve an accuracy of <2μm comparable to SEM.

scholarly journals Facile fabrication of graphene-based high-performance microsupercapacitors operating at high temperature of 150 oC

2021 ◽  
Author(s):  
Viktoriia Mishukova ◽  
Nicolas Boulanger ◽  
Artem Iakunkov ◽  
Szymon Sollami Delekta ◽  
Xiaodong Zhuang ◽  
...  
Keyword(s):  
High Temperature ◽  
Energy Storage ◽  
High Performance ◽  
Electronic Circuits ◽  
Industry Applications ◽  
Facile Fabrication ◽  
On Chip

Many industry applications require electronic circuits and systems to operate at high temperature over 150 oC. Although planar microsupercapacitors (MSCs) have great potential for miniaturized on-chip integrated energy storage components,...

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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