A radiation hardened SRAM cell design in PD-SOI CMOS technology

Author(s):  
Yiqi. Wang ◽  
Ying. Li ◽  
Fazhan. Zhao ◽  
Mengxin. Liu ◽  
Zhengsheng. Han
2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.


Integration ◽  
2018 ◽  
Vol 63 ◽  
pp. 56-63
Author(s):  
Even Låte ◽  
Trond Ytterdal ◽  
Snorre Aunet

2021 ◽  
Vol 125 ◽  
pp. 114376
Author(s):  
Yinghuan Lv ◽  
Qing Wang ◽  
Hao Ge ◽  
Tiantian Xie ◽  
Jing Chen

Author(s):  
JianAn Wang ◽  
Xue Wu ◽  
Haonan Tian ◽  
Lixiang Li ◽  
Shuting Shi ◽  
...  

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