The design of a new spiral inductor balun used in RF/MW based on 0.13μm CMOS process

Author(s):  
Jie Wang ◽  
Wenjun Zhang ◽  
Ruinan Chang ◽  
Zhiping Yu
Keyword(s):  
2011 ◽  
Vol 135-136 ◽  
pp. 918-923 ◽  
Author(s):  
Qing Hua Li

A structure of multi-layer spiral inductor having parallel and series branches of the metal strip was designed for fully-integrated DC-DC converters. As the result that the parallel branching structure greatly reduced the series resistance and the series branching structure greatly improved the series inductance of the inductor, the structure can achieve quality factor and current capability enhancement while compatible with conventional CMOS process. The quality factor was quantitatively analyzed with a scalable model and its origin was investigated at a structural point of view. From the experiment results, the substrate effects can be neglected in the interesting frequency range, 50MHz -500MHz, and the quality factor is enhanced beyond the additional parasitic capacitance.


2010 ◽  
Vol 13 (3) ◽  
pp. 189-192 ◽  
Author(s):  
S.M. Chen ◽  
Y.K. Fang ◽  
C.S. Lin ◽  
Y.T. Chiang ◽  
F.R. Juang ◽  
...  

2009 ◽  
Vol 16 (7) ◽  
pp. 1175-1179 ◽  
Author(s):  
D. K. Jair ◽  
Ming Chun Hsieh ◽  
C. S. Lin

2014 ◽  
Vol 609-610 ◽  
pp. 1503-1507
Author(s):  
Chong Ying Lu ◽  
Jian Hua Li ◽  
Li Xin Xu ◽  
Zhi Gang Wang

The radio frequency (RF) performances of MEMS suspended spiral inductor under high overload environments are studied. Firstly, a suspended spiral inductor and its MEMS surface micromachining process which is compatible with CMOS process are developed. Then, the mechanical responses and RF performances of the inductor are simulated by ANSYS and HFSS, respectively. The simulation results show that, as the overload increases, the inductance and quality factor decrease significantly when the frequency band is closed to the resonant frequency but have no significant change when the frequency band is much lower than resonant frequency; the resonant frequency of the suspended inductor decreases monotonically with the increase of overload. A modified lumped parameter model is utilized to illustrate the simulation results, which theoretically indicates that the substrate loss is more severe than the ohmic loss as the overload increases.


2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.


2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  

Sign in / Sign up

Export Citation Format

Share Document