Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm

2021 ◽  
Author(s):  
Roberto Andrino Robles ◽  
Tomochika Harada ◽  
Michio Yokoyama
Keyword(s):  
Input Frequency ◽  
Frequency Range

scholarly journals NEURAL EXCITABILITY, SPIKING AND BURSTING

2000 ◽  
Vol 10 (06) ◽  
pp. 1171-1266 ◽  
Author(s):  
EUGENE M. IZHIKEVICH
Keyword(s):  
Action Potentials ◽  
Bifurcation Theory ◽  
Low Frequency ◽  
Input Frequency ◽  
Frequency Range ◽  
Saddle Node Bifurcation ◽  
Neural Excitability ◽  
Rest State ◽  
Computational Properties

Bifurcation mechanisms involved in the generation of action potentials (spikes) by neurons are reviewed here. We show how the type of bifurcation determines the neuro-computational properties of the cells. For example, when the rest state is near a saddle-node bifurcation, the cell can fire all-or-none spikes with an arbitrary low frequency, it has a well-defined threshold manifold, and it acts as an integrator; i.e. the higher the frequency of incoming pulses, the sooner it fires. In contrast, when the rest state is near an Andronov–Hopf bifurcation, the cell fires in a certain frequency range, its spikes are not all-or-none, it does not have a well-defined threshold manifold, it can fire in response to an inhibitory pulse, and it acts as a resonator; i.e. it responds preferentially to a certain (resonant) frequency of the input. Increasing the input frequency may actually delay or terminate its firing. We also describe the phenomenon of neural bursting, and we use geometric bifurcation theory to extend the existing classification of bursters, including many new types. We discuss how the type of burster defines its neuro-computational properties, and we show that different bursters can interact, synchronize and process information differently.

Analog-Based CMOS Duty Cycle Corrector with 50–800 MHz Operating Range

2015 ◽  
Vol 24 (07) ◽  
pp. 1550100
Author(s):  
Rui Ma ◽  
Zhangming Zhu ◽  
Maliang Liu ◽  
Ping Gan ◽  
Yintang Yang
Keyword(s):  
High Resolution ◽  
Duty Cycle ◽  
High Speed ◽  
Delay Line ◽  
Cmos Process ◽  
Input Frequency ◽  
Frequency Range ◽  
Locking Range ◽  
Layout Area ◽  
Forward Body Bias

In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 μm 1.8 V standard CMOS process show that output duty cycle error is less than ±1% over an input frequency range of 50–800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 × 0.21 mm2.

scholarly journals A Low-voltage Programmable Frequency Divider with Wide Input Frequency Range

2018 ◽  
Vol 17 ◽  
pp. 01007
Author(s):  
Yilong Liao ◽  
Xiangning Fan
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Input Frequency ◽  
Maximum Frequency ◽  
Frequency Division ◽  
Frequency Range ◽  
Division Ratio ◽  
Custom Design ◽  
Programmable Frequency Divider

A low-voltage programmable frequency divider with wide input frequency range is fabricated in standard 0.18µm TSMC RF CMOS technology and presented in this paper. Considering the frequency division ratio of dual-modulus prescaler is relatively smaller, a programmable divider with full custom design is used to increase the frequency division ratio and the maximum operating frequency. The frequency division ratio of the programmable frequency divider covers from 64 to 255. And the measured results show that the programmable divider works correctly when the input frequency varies from 0.5 GHz to 6.0 GHz, with 1V supply. Besides, the power consumption is 3.5 mA at the maximum frequency of 6.0 GHz.

Current Mode Maximum and Minimum Circuit

2014 ◽  
Vol 577 ◽  
pp. 478-481 ◽  
Author(s):  
Han Wang ◽  
Yi Cheng Zeng ◽  
Zhi Jun Li
Keyword(s):  
Integrated Circuit ◽  
Current Mode ◽  
Cmos Technology ◽  
Maximum Output ◽  
Input Frequency ◽  
Design Technique ◽  
Frequency Range ◽  
Artificial Neural Network Ann ◽  
Winner Take All ◽  
Take All

A new current mode circuit which can maintain the maximum output and minimum output at the same time is presented in this paper. The design technique is achieved by the combination of trans linear loop, winner take all (WTA) circuit and loser take all (LTA) circuit. Therefore, the proposed circuit can be more practical than conventional circuits and can be easily designed in 0.5 μm CMOS technology for CSMC. Analysis and simulations of WTA and LTA circuit have been shown to display the usability of the proposed circuit, where the input frequency range is around 10 MHz. The proposed circuit can also play a neuron role in artificial neural network (ANN) implemented in the form of an integrated circuit.

An inductorless active mixer using stacked nMOS/pMOS configuration and LO shaping technique

2018 ◽  
Vol 32 (11) ◽  
pp. 1850129 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Xuebing Wang ◽  
Hongpeng Chen
Keyword(s):  
Noise Figure ◽  
Power Level ◽  
Cmos Process ◽  
Conversion Gain ◽  
Input Frequency ◽  
Frequency Range ◽  
Shaping Technique ◽  
Active Mixer ◽  
Down Conversion ◽  
Second Order Nonlinearity

In this paper, a CMOS active down-conversion mixer is presented for wideband applications. Specifically, a LO generation chain is suggested to convert AC LO signal to shaped trapezoid burst, which reduces the sinusoidal LO power level requirement by the mixer. The current-reuse technique by stacked nMOS/pMOS architecture is used to save the power consumption of the circuit. Moreover, this complementary configuration is also employed to compensate second-order nonlinearity of the circuit. Implemented in a 0.18-[Formula: see text]m CMOS process, post-simulations show that, driven by only −10 dBm sinusoidal LO signal, the proposed inductorless mixer provides a maximal conversion gain of 15.7 dB and a noise figure (NF) of 9.1–12 dB across RF input frequency range 0.5–1.6 GHz. The IIP3 and IP1dB of 3.5 dBm and −4.8 dBm are obtained, respectively. The mixer core only consumes 3.6 mW from a 1.8-V supply.

scholarly journals Reducing interaural tonotopic mismatch preserves binaural unmasking in cochlear implant simulations of single-sided deafness

2020 ◽  
Author(s):  
Elad Sagi ◽  
Mahan Azadpour ◽  
Jonathan Neukam ◽  
Nicole Hope Capach ◽  
Mario A. Svirsky
Keyword(s):  
Cochlear Implant ◽  
Low Frequency ◽  
Spatial Separation ◽  
Binaural Hearing ◽  
Normal Hearing ◽  
Input Frequency ◽  
Frequency Range ◽  
Speech Processor ◽  
Frequency Information ◽  
Single Sided Deafness

Binaural unmasking, a key feature of normal binaural hearing, refers to the improved intelligibility of masked speech by adding masking noise that facilities perceived spatial separation of target and masker. A question particularly relevant for cochlear implant users with single-sided deafness (SSD-CI) is whether binaural unmasking can still be achieved if the additional masking is distorted. Adding the CI restores some aspects of binaural hearing to these listeners, although binaural unmasking remains limited. Notably, these listeners may experience a mismatch between the frequency information perceived through the CI and that perceived by their normal hearing ear. Employing acoustic simulations of SSD-CI with normal hearing listeners, the present study confirms a previous simulation study that binaural unmasking is severely limited when interaural frequency mismatch between the input frequency range and simulated place of stimulation exceeds 1-2 mm. The present study also shows that binaural unmasking is largely retained when the input frequency range is adjusted to match simulated place of stimulation, even at the expense of removing low-frequency information. This result bears implication for the mechanisms driving the type of binaural unmasking of the present study, as well as for mapping the frequency range of the CI speech processor in SSD-CI users.

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