A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

Unlimited Power Division Ratio of Microstrip Balanced-to-Unbalanced Gysel-Type Arbitrary Power Divider

A microstrip balanced-to-unbalanced (BTU) Gysel-type arbitrary power divider without the high-impedance transmission-line (TL) section is proposed to eliminate the power division ratio (PDR) limit of the conventional microstrip BTU power dividers. The proposed circuit includes five moderate-impedance TLs having the same characteristic impedance in addition to a grounded resistor. The arbitrary PDR is easily obtained by varying the electrical length of the TLs without changing the characteristic impedances, especially the large PDR, which is difficult to achieve by means of conventional BTU power dividers. When the PDR is ∞, the proposed circuit becomes a balun. The closed-form design equations are derived and discussed. To verify the proposed circuit, three prototypes I, II, and III are designed and fabricated for PDRs of 10 dB, 20 dB, and ∞ dB, respectively. The measured PDRs are in good agreement with the simulations. The measured isolation between the output ports is higher than 31 dB for prototypes I and II. The measured insertion loss of the balun prototype is 0.194 dB. Furthermore, the common-mode suppression of greater than 32 dB and the return loss of higher than 22 dB are obtained for various PDRs.