scholarly journals A Low-voltage Programmable Frequency Divider with Wide Input Frequency Range

2018 ◽  
Vol 17 ◽  
pp. 01007
Author(s):  
Yilong Liao ◽  
Xiangning Fan
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Input Frequency ◽  
Maximum Frequency ◽  
Frequency Division ◽  
Frequency Range ◽  
Division Ratio ◽  
Custom Design ◽  
Programmable Frequency Divider

A low-voltage programmable frequency divider with wide input frequency range is fabricated in standard 0.18µm TSMC RF CMOS technology and presented in this paper. Considering the frequency division ratio of dual-modulus prescaler is relatively smaller, a programmable divider with full custom design is used to increase the frequency division ratio and the maximum operating frequency. The frequency division ratio of the programmable frequency divider covers from 64 to 255. And the measured results show that the programmable divider works correctly when the input frequency varies from 0.5 GHz to 6.0 GHz, with 1V supply. Besides, the power consumption is 3.5 mA at the maximum frequency of 6.0 GHz.

A wide division-ratio range programmable frequency divider with driving-capability improved

2010 ◽  
Vol 63 (3) ◽  
pp. 509-514 ◽  
Author(s):  
Shengyang Wang ◽  
Jianhui Wu ◽  
Meng Zhang ◽  
Fuqing Huang ◽  
Ling Tang ◽  
...  
Keyword(s):  
Frequency Divider ◽  
Division Ratio ◽  
Ratio Range ◽  
Driving Capability ◽  
Programmable Frequency Divider

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

Current Mode Maximum and Minimum Circuit

2014 ◽  
Vol 577 ◽  
pp. 478-481 ◽  
Author(s):  
Han Wang ◽  
Yi Cheng Zeng ◽  
Zhi Jun Li
Keyword(s):  
Integrated Circuit ◽  
Current Mode ◽  
Cmos Technology ◽  
Maximum Output ◽  
Input Frequency ◽  
Design Technique ◽  
Frequency Range ◽  
Artificial Neural Network Ann ◽  
Winner Take All ◽  
Take All

A new current mode circuit which can maintain the maximum output and minimum output at the same time is presented in this paper. The design technique is achieved by the combination of trans linear loop, winner take all (WTA) circuit and loser take all (LTA) circuit. Therefore, the proposed circuit can be more practical than conventional circuits and can be easily designed in 0.5 μm CMOS technology for CSMC. Analysis and simulations of WTA and LTA circuit have been shown to display the usability of the proposed circuit, where the input frequency range is around 10 MHz. The proposed circuit can also play a neuron role in artificial neural network (ANN) implemented in the form of an integrated circuit.

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