Flashover Fault Localization for Gas Insulated Line Based on Steep Wave Sensing

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

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Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0233 ◽

2010 ◽

Author(s):

Kuo Hsiung Chen ◽

Wen Sheng Wu ◽

Yu Hsiang Shu ◽

Jian Chan Lin

Keyword(s):

Failure Analysis ◽

Failure Mechanisms ◽

Fault Localization ◽

Resistance Change ◽

The Real ◽

Analysis Techniques ◽

Analysis Technique ◽

Leakage Failure ◽

Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

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Fault Localization of Power-Ground Short via Signal Injection and Oscilloscope Technique

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0202 ◽

2010 ◽

Author(s):

Binh Nguyen

Keyword(s):

Low Cost ◽

Short Circuit ◽

Fault Localization ◽

Fault Isolation ◽

Test Apparatus ◽

Good Working ◽

Signal Injection ◽

Set Up ◽

Non Destructive ◽

Short Circuit Condition

Abstract For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.

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Enhanced Detection Sensitivity with Pulsed Laser Digital Signal Integration Algorithm

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0234 ◽

2006 ◽

Author(s):

A.C.T. Quah ◽

J.C.H. Phang ◽

L.S. Koh ◽

S.H. Tan ◽

C.M. Chua

Keyword(s):

Fault Localization ◽

Pulsed Laser ◽

Digital Signal ◽

Detection Sensitivity ◽

Signal Integration ◽

Laser Operation ◽

Frequency Range ◽

Integration Algorithm ◽

Detection Systems ◽

Lock In

Abstract This paper describes a pulsed laser induced digital signal integration algorithm for pulsed laser operation that is compatible with existing ac-coupled and dc-coupled detection systems for fault localization. This algorithm enhances laser induced detection sensitivity without a lock-in amplifier. The best detection sensitivity is achieved at a pulsing frequency range between 500 Hz to 1.5 kHz. Within this frequency range, the algorithm is capable of achieving more than 9 times enhancement in detection sensitivity.

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Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0413 ◽

2003 ◽

Author(s):

Jon C. Lee ◽

J. H. Chuang

Keyword(s):

Atomic Force Microscopy ◽

Integrated Circuits ◽

Fault Localization ◽

Electrical Characterization ◽

Conductive Atomic Force Microscopy ◽

Force Microscopy ◽

Atomic Force ◽

Optical Electron ◽

Defect Isolation ◽

Voltage Contrast

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

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Concepts for In Situ Diagnostics in Analog Microelectronic Circuits

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0301 ◽

2007 ◽

Author(s):

Ted Kolasa ◽

Alfredo Mendoza

Keyword(s):

Analog Circuits ◽

System Architecture ◽

Analog Circuit ◽

Fault Localization ◽

Diagnostic System ◽

Diagnostic Capability ◽

Common Signal ◽

Diagnostic Capabilities ◽

In Situ Diagnostics

Abstract Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.

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A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0100 ◽

2014 ◽

Author(s):

Gwee Hoon Yen ◽

Ng Kiong Kay

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Flip Chip ◽

Fault Localization ◽

Cost Effective ◽

Fault Isolation ◽

Voltage Contrast ◽

Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

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