A 3-5GHz gm-Boosted Common-Gate CMOS UWB LNA with a Common-Source Auxiliary circuit

2008 ◽  
Author(s):  
Liu Jinhua ◽  
Chen Guican ◽  
Zhang Hong
Keyword(s):  
Common Source ◽  
Common Gate ◽  
Auxiliary Circuit

2.2–4.6-GHz Active Quasi-Circulator with > 24-dB Transmit–Receive Isolation

2019 ◽  
Vol 29 (05) ◽  
pp. 2050077
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Danish Kaleem ◽  
Zhi-Gong Wang ◽  
Keping Wang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
The Body ◽  
Common Source ◽  
Cmos Process ◽  
Secondary Effects ◽  
Body Effect ◽  
Chip Area ◽  
Common Gate ◽  
Loading Effects ◽  
Better Than

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[Formula: see text]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [Formula: see text] dB between transmitter-to-antenna ports ([Formula: see text]) and of [Formula: see text] dB between antenna-to-receiver ports ([Formula: see text]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([Formula: see text]) is better than 24 dB with a maximum value of 29.5[Formula: see text]dB @ 3.6[Formula: see text]GHz. The power dissipation of the proposed AQC is 40[Formula: see text]mW and it covers an active chip area of 0.677[Formula: see text]mm2.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

Extended Characterization of the Common-Source and Common-Gate Amplifiers Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

2014 ◽  
Vol 157 (1) ◽  
pp. 71-80
Author(s):  
Mitchell R. Hunt ◽  
Rana Sayyah ◽  
Cody Mitchell ◽  
Crystal L. McCartney ◽  
Todd C. Macleod ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Common Source ◽  
Common Gate ◽  
The Common ◽  
Effect Transistor

scholarly journals A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

2018 ◽  
Vol 8 (4) ◽  
pp. 42
Author(s):  
Vikram Singh ◽  
Sandeep Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Average Power ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Power Gain ◽  
Wireless Applications ◽  
Common Gate ◽  
Noise Amplifier

An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

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