A Modified Noise Analysis of a Common Source  ̶ Common Gate Low Noise Transconductance Amplifier for Sub-micron Technologies

An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

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A Single-To-Differential LNA using Differential Active Inductor for GPS Applications

Frequenz ◽

10.1515/freq-2012-0071 ◽

2013 ◽

Vol 67 (1-2) ◽

Author(s):

Hojjat Babaei Kia ◽

Abu Khari A'ain

Keyword(s):

Cmos Technology ◽

Low Noise ◽

Low Noise Amplifier ◽

Common Source ◽

Active Inductor ◽

Active Load ◽

Common Gate ◽

Noise Amplifier ◽

On Chip

AbstractThis paper presents the design of a single-ended input, differential output low noise amplifier for GPS applications in 0.18 µm CMOS technology. This Low Noise Amplifier (LNA) is composed of a common source (CS) amplifier adopted with a common gate, common source (CGCS) balun load. Instead of spiral on-chip inductor, a differential active inductor circuit (DAI) is used as an active load of balun and also

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A 3–14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126619500567 ◽

2019 ◽

Vol 28 (04) ◽

pp. 1950056 ◽

Cited By ~ 3

Author(s):

Vikram Singh ◽

Sandeep Kumar Arya ◽

Manoj Kumar

Keyword(s):

Reflection Coefficient ◽

Noise Figure ◽

Impedance Matching ◽

Low Noise ◽

Ultra Wideband ◽

Common Source ◽

Cmos Process ◽

Frequency Range ◽

Continuous Growth ◽

Common Gate

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

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Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

International Journal of Advanced Research in Science, Communication and Technology ◽

10.48175/ijarsct-1815 ◽

2021 ◽

pp. 85-94

Author(s):

Dr. Rashmi S B ◽

Mr. Raghavendra B ◽

Mr. Sanketh V

Keyword(s):

Reflection Coefficient ◽

Noise Figure ◽

Cmos Technology ◽

Low Noise ◽

Low Noise Amplifier ◽

Ultra Wideband ◽

Common Source ◽

Frequency Range ◽

Common Gate ◽

Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

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Noise analysis of the CG-CS low noise transconductance amplifier

2011 IEEE International Conference of Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2011.6117630 ◽

2011 ◽

Author(s):

Jiangtao Xu ◽

Carlos E. Saavedra ◽

Guican Chen

Keyword(s):

Noise Analysis ◽

Low Noise ◽

Transconductance Amplifier

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A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

Journal of Circuits System and Computers ◽

10.1142/s0218126618500032 ◽

2017 ◽

Vol 27 (01) ◽

pp. 1850003 ◽

Cited By ~ 1

Author(s):

Shaomin Huang ◽

Zhongpan Yang ◽

Chao Hua

Keyword(s):

Power Dissipation ◽

Noise Figure ◽

Supply Voltage ◽

Low Noise ◽

Common Source ◽

Cmos Process ◽

Measurement Results ◽

Common Gate ◽

Noise Amplifier ◽

Noise Canceling

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

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S-Parameter Comparison of Common Source and Common Gate Low Noise Amplifier

International Journal of Computer Applications ◽

10.5120/21335-4331 ◽

2015 ◽

Vol 120 (19) ◽

pp. 15-18 ◽

Cited By ~ 1

Author(s):

Mohit Dayal ◽

Abhishek Kumar

Keyword(s):

Low Noise ◽

Low Noise Amplifier ◽

Common Source ◽

S Parameter ◽

Common Gate ◽

Noise Amplifier

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A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

Electronics ◽

10.3390/electronics10091078 ◽

2021 ◽

Vol 10 (9) ◽

pp. 1078

Author(s):

Thi Thuy Pham ◽

Dongmin Kim ◽

Seo-Hyeong Jeong ◽

Junghyup Lee ◽

Donggu Im

Keyword(s):

Power Consumption ◽

High Efficiency ◽

Supply Voltage ◽

Current Source ◽

Low Noise ◽

The Body ◽

Common Source ◽

Conversion Gain ◽

Input Transistor ◽

Envelope Detector

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

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