scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

scholarly journals Design of Common-gate with Common-source Active Balun for WiMAX Receiver Front-end

2019 ◽  
pp. 1-9
Author(s):  
Frederick Ray I. Gomez ◽  
Maria Theresa G. De Leon ◽  
John Richard E. Hizon
Keyword(s):  
Phase Difference ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun ◽  
The Common

This paper presents a design and simulation study of a common-gate with common-source active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) process.  The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V.  Measurements are taken for parameters namely gain difference, phase difference, and noise figure.  The common-source active balun design achieved a minimal gain difference of  0.04 dB, phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past active balun designs and researches.  The design eventually achieved a low power consumption of 4.45 mW.

scholarly journals Differential Active Balun Design for WiMAX Applications

2019 ◽  
pp. 1-8
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Active Balun

The paper presents a design and simulation study of a differential active balun circuit implemented in a standard 90 nm complementary metal-oxide semiconductor (CMOS) process.  The active balun design is intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8 GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  The differential active balun design achieved gain difference of less than 0.23 dB, phase difference of 180° ± 3.4°, and noise figure of 9.78 dB, which are comparable to past active balun designs and researches.  Lastly, the design achieved a low power consumption of 3.6 mW.

scholarly journals Design of Common-Source/Drain Active Balun Using 90nm CMOS Technology

2019 ◽  
pp. 1-9
Author(s):  
Frederick Ray I. Gomez ◽  
Maria Theresa G. De Leon ◽  
John Richard E. Hizon
Keyword(s):  
Phase Difference ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Active Balun ◽  
The Common

This research paper presents a design and study of a common-source/drain active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology.  The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8GHz and supply voltage of 1V.  Measurements are taken for parameters namely gain difference, phase difference, and noise figure.  The common-source active balun design achieved a minimal gain difference of 0.016dB, phase difference of 180° ± 7.1°, and noise figure of 7.42-9.85dB, which are comparable to past active balun designs and researches.  The design eventually achieved a low power consumption of 2.56mW.

A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

2017 ◽  
Vol 27 (01) ◽  
pp. 1850003 ◽  
Author(s):  
Shaomin Huang ◽  
Zhongpan Yang ◽  
Chao Hua
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Measurement Results ◽  
Common Gate ◽  
Noise Amplifier ◽  
Noise Canceling

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

scholarly journals A 65 nm Duplex Transconductance Path Up-Conversion Mixer for 24 GHz Automotive Short-Range Radar Sensor Applications

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 594
Author(s):  
Tahesin Samira Delwar ◽  
Abrar Siddique ◽  
Manas Ranjan Biswal ◽  
Prangyadarsini Behera ◽  
Yeji Choi ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Short Range ◽  
Noise Figure ◽  
Supply Voltage ◽  
Common Source ◽  
Cmos Process ◽  
Radar Sensor ◽  
Sensor Applications ◽  
The Common ◽  
24 Ghz

A 24 GHz highly-linear upconversion mixer, based on a duplex transconductance path (DTP), is proposed for automotive short-range radar sensor applications using the 65-nm CMOS process. A mixer with an enhanced transconductance stage consisting of a DTP is presented to improve linearity. The main transconductance path (MTP) of the DTP includes a common source (CS) amplifier, while the secondary transconductance path (STP) of the DTP is implemented as an improved cross-quad transconductor (ICQT). Two inductors with a bypass capacitor are connected at the common nodes of the transconductance stage and switching stage of the mixer, which acts as a resonator and helps to improve the gain and isolation of the designed mixer. According to the measured results, at 24 GHz the proposed mixer shows that the linearity of output 1-dB compression point (OP1dB) is 3.9 dBm. And the input 1-dB compression point (IP1dB) is 0.9 dBm. Moreover, a maximum conversion gain (CG) of 2.49 dB and a noise figure (NF) of 3.9 dB is achieved in the designed mixer. When the supply voltage is 1.2 V, the power dissipation of the mixer is 3.24 mW. The mixer chip occupies an area of 0.42 mm2.

scholarly journals Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb/s Optical Receivers

2015 ◽  
Vol 14 (5) ◽  
pp. 5661-5686
Author(s):  
Essra E. Al-Bayati ◽  
R. S. Fyath
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Optical Receivers ◽  
Distributed Amplifier ◽  
Design Scheme

The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. Thesimulation is performed using AWR Microwave Office (version 10).

A 3–14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS

2019 ◽  
Vol 28 (04) ◽  
pp. 1950056 ◽  
Author(s):  
Vikram Singh ◽  
Sandeep Kumar Arya ◽  
Manoj Kumar
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Impedance Matching ◽  
Low Noise ◽  
Ultra Wideband ◽  
Common Source ◽  
Cmos Process ◽  
Frequency Range ◽  
Continuous Growth ◽  
Common Gate

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

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