Abstract. In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area. The rising electrical fields bring up reliability problems, such as hot carrier injection. Also other long term degradation mechanisms like Negative Bias Temperature Instability (NBTI) come into the focus of circuit design. Along with process device parameter variations (threshold voltage, mobility), variations due to the degradation of devices form a big challenge for designers to build circuits that both yield high under the influence of process variations and remain functional with respect to long term device drift. In this work we present the influence of long term degradation and process variations on the performance of SRAM core-cells and parametric yield of SRAM arrays. For different use cases we show the performance degradation depending on temperature and supply voltage.
Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs
