Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel

Author(s):  
Ya-Chi Cheng ◽  
Hung-Bin Chen ◽  
Chi-Shen Shao ◽  
Jun-Ji Su ◽  
Yung-Chun Wu ◽  
...  
2020 ◽  
Vol 91 (3) ◽  
pp. 30201
Author(s):  
Hang Yu ◽  
Jianlin Zhou ◽  
Yuanyuan Hao ◽  
Yao Ni

Organic thin film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8BTBT) and copper (Cu) electrodes were fabricated. For improving the electrical performance of the original devices, the different modifications were attempted to insert in three different positions including semiconductor/electrode interface, semiconductor bulk inside and semiconductor/insulator interface. In detail, 4,4′,4′′-tris[3-methylpheny(phenyl)amino] triphenylamine (m-MTDATA) was applied between C8BTBTand Cu electrodes as hole injection layer (HIL). Moreover, the fluorinated copper phthalo-cyanine (F16CuPc) was inserted in C8BTBT/SiO2 interface to form F16CuPc/C8BTBT heterojunction or C8BTBT bulk to form C8BTBT/F16CuPc/C8BTBT sandwich configuration. Our experiment shows that, the sandwich structured OTFTs have a significant performance enhancement when appropriate thickness modification is chosen, comparing with original C8BTBT devices. Then, even the low work function metal Cu was applied, a normal p-type operate-mode C8BTBT-OTFT with mobility as high as 2.56 cm2/Vs has been fabricated.


The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.


Author(s):  
Srikant Kumar Mohanty ◽  
ChienHung Wu ◽  
Shih-Ho Chang ◽  
K-M Chang

Abstract In this study, we investigated the effect of microwave-irradiation annealing (MWA) and thermal furnace annealing (FA) in oxygen ambient on the active channel layer of p-type tin-oxide (SnO) thin-film transistors (TFTs). At very low source-drain voltage of -0.1 V, the MWA at 1200 W and FA at 300 °C samples have exhibited significant improvement in the electrical characteristics such as subthreshold swing (SS) of 0.93 and 0.485 V/dec, the Ion/Ioff ratio of 1.65 x 104and 3.07 x 104, the field-effect mobility (μFE) of 0.16 and 0.26 cm2/V·s and ultra-low off-state current of 1.9 pA and 2.0 pA respectively. The observed performance enhancement was mainly attributed to the reduction of interface trap density (Nt) by tuning the power of MWA and optimizing the temperature in FA. From the result, we observed the optical band gap (Eg) increased by 6% in FA, and 12% in MWA, which confirms improved crystallinity and reduction of defect states. Additionally, a low thermal budget microwave anneal process has shown high transmittance of more than 86% in the visible region (380-700 nm). The physical characterization indicates the partial phase transformation of SnO to SnO2 with retaining p-type conductivity in both annealing process. The results demonstrate that both the annealing process could be highly promising to be used in the complementary logic circuits of new generation flexible/transparent displays.


2015 ◽  
Vol 45 (3) ◽  
pp. 1240-1244 ◽  
Author(s):  
Liangwei Fu ◽  
Junyou Yang ◽  
Qinghui Jiang ◽  
Ye Xiao ◽  
Yubo Luo ◽  
...  

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