High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

Author(s):  
Chung-Hao Tsai ◽  
Jeng-Shien Hsieh ◽  
Wei-Heng Lin ◽  
Liang-Ju Yen ◽  
Jeng-Nan Hung ◽  
...  
2019 ◽  
Vol 61 (9) ◽  
pp. 2210-2213
Author(s):  
Jong‐Min Yook ◽  
Sanghoon Sim ◽  
Bok‐Ju Park ◽  
Dongsu Kim ◽  
Young‐Joon Kim

2001 ◽  
Author(s):  
Chirag Patel ◽  
Kevin P. Martin ◽  
James D. Meindl

Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.


Author(s):  
Christianto C. Liu ◽  
Shuo-Mao Chen ◽  
Feng-Wei Kuo ◽  
Huan-Neng Chen ◽  
En-Hsiang Yeh ◽  
...  

Author(s):  
Steffen Kroehnert ◽  
André Cardoso ◽  
Steffen Kroehnert ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
...  

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.


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