Compliant Wafer Level Package

2001 ◽  
Author(s):  
Chirag Patel ◽  
Kevin P. Martin ◽  
James D. Meindl
Keyword(s):  
Performance Analysis ◽  
Integrated Circuits ◽  
High Performance ◽  
Wafer Level ◽  
Electronic Products ◽  
Packaging Technology ◽  
Technology Roadmap ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Wafer Level Package

Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.

Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

2008 ◽  
Vol 1068 ◽  
Author(s):  
Augusto Gutierrez-Aitken ◽  
Patty Chang-Chien ◽  
Bert Oyama ◽  
Kelly Tornquist ◽  
Khanh Thai ◽  
...  
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Heterogeneous Integration ◽  
Space Technology ◽  
Wafer Level ◽  
Selective Epitaxial Growth ◽  
Wafer Level Packaging ◽  
Design Flexibility ◽  
Systems Requirements ◽  
And Performance

ABSTRACTTo meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.

Wafer level packaging of compliant, chip size ICs

2000 ◽  
Vol 17 (2) ◽  
pp. 23-27 ◽  
Author(s):  
Joseph Fjelstad ◽  
Thomas DiStefano ◽  
Anthony Faraci
Keyword(s):  
Integrated Circuits ◽  
Wide Area ◽  
Wafer Level ◽  
Easy Method ◽  
Future Directions ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
Chip Size ◽  
Mass Assembly ◽  
Ic Package

The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVETM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint remains constant. The technology is based on concepts that allow for the mass assembly and production of compliant packages both directly on the wafer and in “virtual wafer” format where individual chips are bonded directly to the flexible pellicle. This paper examines this important new packaging technology concept in terms of the process and device and the implications and future directions the technology is likely to take.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Suspended high Q integrated inductor by wafer level packaging technology

2013 ◽  
Vol 21 (1) ◽  
pp. 215-219 ◽  
Author(s):  
M. Han ◽  
S. F. Wang ◽  
G. W. Xu ◽  
Le Luo
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
High Q ◽  
Integrated Inductor ◽  
Wafer Level Packaging

High Quality Integrated Inductor in Fan-out Wafer-Level Packaging Technology for mm-Wave Applications

2021 ◽  
Author(s):  
Kavin Senthil Murugesan ◽  
Mykola Chernobryvko ◽  
Sherko Zinal ◽  
Marco Rossi ◽  
Ivan Ndip ◽  
...  
Keyword(s):  
Wafer Level ◽  
High Quality ◽  
Packaging Technology ◽  
Integrated Inductor ◽  
Wafer Level Packaging

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

scholarly journals Wafer Level Packaging Technology Applied to Pixel Detectors

2021 ◽  
Vol 9 ◽  
Author(s):  
Paolo Conci ◽  
Giovanni Darbo ◽  
Andrea Gaudiello ◽  
Claudia Gemme ◽  
Stefano Girardi ◽  
...  
Keyword(s):  
High Energy Physics ◽  
High Energy ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Technical Requirements ◽  
Pixel Detectors ◽  
Single Sensor ◽  
Wafer Processing ◽  
Wafer Level Package ◽  
Energy Physics

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

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