An all-CMOS low supply voltage temperature sensor front-end with error correction techniques

Author(s):  
Li Lu ◽  
Changzhi Li ◽  
Jinghong Chen
2012 ◽  
Vol 48 (16) ◽  
pp. 987-988 ◽  
Author(s):  
Li Lu ◽  
Jinghong Chen ◽  
Changzhi Li

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.


1992 ◽  
Vol 27 (4) ◽  
pp. 583-588 ◽  
Author(s):  
Y. Miyawaki ◽  
T. Nakayama ◽  
S. Kobayashi ◽  
N. Ajika ◽  
M. Ohi ◽  
...  

Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .


2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.


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