Eye diagram estimation of 8B/10B encoded high-speed serial link for signal integrity test using silicone rubber socket

2016 ◽  
Author(s):  
Junyong Park ◽  
Jonghoon J. Kim ◽  
Heegon Kim ◽  
Joungho Kim ◽  
Michael Bae ◽  
...  
Keyword(s):  
Silicone Rubber ◽  
High Speed ◽  
Signal Integrity ◽  
Integrity Test ◽  
Serial Link ◽  
Eye Diagram

Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

SerDes Design and Modeling over 25+ Gb/s Serial Link

2011 ◽  
Vol 2011 (1) ◽  
pp. 000044-000060
Author(s):  
Pervez M. Aziz ◽  
Adam Healey ◽  
Cathy Liu ◽  
Freeman Zhong ◽  
Alex Zabroda
Keyword(s):  
High Speed ◽  
Forward Error Correction ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Systems Modeling ◽  
Behavioral Models ◽  
Noisy Environments ◽  
Serial Link ◽  
Link Performance ◽  
Forward Error

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.

Twisted-Overlap Differential-Pair Approach to Increase Available Layout Space and Reliability in PCB Design

2013 ◽  
Vol 284-287 ◽  
pp. 2531-2537
Author(s):  
Chiu Ching Tuan ◽  
Sun Yen Tan ◽  
Wen Tzeng Huang ◽  
Hung Li Tseng
Keyword(s):  
High Speed ◽  
Signal Integrity ◽  
Great Benefit ◽  
Electronic Products ◽  
Eye Diagram ◽  
Space Requirement ◽  
Pcb Design ◽  
Differential Pair

Modern electronic products require many high-speed differential pairs which require more layout space in PCB design. We propose a twisted-overlap differential-pair (TODP) structure to obtain more routing space and achieve better signal integrity in this study. TODP reduces the layout space requirement by about 25% compared with that required by traditional differential pairs and the twisted differential lines (TDL) structure [2]. Based on an eye diagram performance the TODP design compared to the traditional and TDL designs can improve the peak-to-peak jitter by 26.5% and 12.2%, the overshoot by 14.3% and 2%, the undershoot by 18.8% and 5%, and the eye width by 2 and 1%, respectively. Our results indicate that TODP may be of great benefit in differential-pair PCB design.

Sign in / Sign up

Export Citation Format

Share Document