Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test

Author(s):  
Youngsu Oh ◽  
Dongmin Han ◽  
Byeongseon Go ◽  
Seungtaek Lee ◽  
Woosik Jeong
2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.


2013 ◽  
Vol 284-287 ◽  
pp. 2531-2537
Author(s):  
Chiu Ching Tuan ◽  
Sun Yen Tan ◽  
Wen Tzeng Huang ◽  
Hung Li Tseng

Modern electronic products require many high-speed differential pairs which require more layout space in PCB design. We propose a twisted-overlap differential-pair (TODP) structure to obtain more routing space and achieve better signal integrity in this study. TODP reduces the layout space requirement by about 25% compared with that required by traditional differential pairs and the twisted differential lines (TDL) structure [2]. Based on an eye diagram performance the TODP design compared to the traditional and TDL designs can improve the peak-to-peak jitter by 26.5% and 12.2%, the overshoot by 14.3% and 2%, the undershoot by 18.8% and 5%, and the eye width by 2 and 1%, respectively. Our results indicate that TODP may be of great benefit in differential-pair PCB design.


Author(s):  
Xiuqin Chu ◽  
Wenting Guo ◽  
Jun Wang ◽  
Feng Wu ◽  
Yuhuan Luo ◽  
...  

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