Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000223-000227 ◽  
Author(s):  
Zhuowen Sun ◽  
Kevin Chen ◽  
Richard Crisp
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Signal Integrity ◽  
Bottom Layer ◽  
Data Rate ◽  
Optimization Techniques ◽  
Network Computing ◽  
Memory Applications ◽  
Type 3

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design. To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used. We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology. Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate >1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

2016 ◽  
Vol 13 (3) ◽  
pp. 128-135
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses ◽  
Low Permittivity

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive

2011 ◽  
Vol 2011 (1) ◽  
pp. 000509-000515 ◽  
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
Solder Joint ◽  
High Speed ◽  
Room Temperature ◽  
Low Cost ◽  
White Paper ◽  
Solder Paste ◽  
Fine Pitch ◽  
Increasing Demand ◽  
The Right ◽  
Device Miniaturization

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process. After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.

Drop Test for Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) Surface Treatment Application That is Suitable to a Low-Cost, Fine Pitch and Easy Fabrication

2009 ◽  
Author(s):  
Junehyeon Ahn ◽  
Hongkwon Kim ◽  
Kangho Byun ◽  
Youngmin Lee ◽  
Donghoon Jang ◽  
...  
Keyword(s):  
Data Acquisition ◽  
Test Performance ◽  
High Speed ◽  
Low Cost ◽  
Electroless Nickel ◽  
Drop Test ◽  
In Situ Data ◽  
Fine Pitch ◽  
Device Reliability

For an application of fine pitch Ball Grid Array (BGA) or Land Grid Array (LGA) packages, ENEPIG is a promising surface finish technology of low cost, fine pitch and easy fabrication. In this paper, we study the drop test, one of the most important items of hand held device reliability test, of ENEPIG surface finished packages. This paper focuses on the drop test performance of a bond between the main board and three kinds of packages. Those packages are designed with a daisy chain for a detection of open/short during the drop test. The main board has a bar type outline and is suitable for an In-Situ data acquisition. Drop tester is composed of a drop test unit, a high speed resistance meter and a data acquisition system (PC). JEDEC Condition B (1,500G and 0.5milliseconds duration time and half-sine pulse) in JESD22-B111 Table 1 or in JESD22-B104-C Table 1 is applied as a test condition. After the drop test, the joint geometry and the intermetallic compound (IMC) of failure samples are analyzed through the cross section method. The result shows no breaks at the solder joint of package side. All breaks, however, are originated from the solder joints of main board side. It is a significant outcome of this work to show no performance difference between ENEPIG and Electrolytic Ni/Au.

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