Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

2019 ◽  
Vol 68 ◽  
pp. 92-101 ◽  
Author(s):  
R. Murugasami ◽  
U.S. Ragupathy
Keyword(s):  
Comparative Analysis ◽  
Power Systems ◽  
Low Power ◽  
High Performance ◽  
Flip Flop ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals A NEW REDUCED CLOCK POWER FLIP-FLOP FOR FUTURE SOC APPLICATIONS

2013 ◽  
pp. 292-295
Author(s):  
MOHAMMADRAFI SHAIK ◽  
LLAPAVULURI ADITYA ABHILASH ◽  
PADALA SRINIVAS
Keyword(s):  
Low Power ◽  
Software Tools ◽  
Data Mapping ◽  
Analysis Software ◽  
Flip Flop ◽  
Novel Technique ◽  
The Future ◽  
Pass Transistor ◽  
Pass Transistor Logic ◽  
New System

In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper we propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.Our proposed which is designed using Pass Transistor Logic (LCPTFF) Low Power Clocked Pass Transistor Flip-Flop system is showing much better output than all other designs as mentioned in the tabulation.The simulations are done using Microwind& DSCH analysis software tools and the result between all those types are listed below.

scholarly journals A Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design In 90nm Cmos Technology

2019 ◽  
Vol 8 (11) ◽  
pp. 3258-3262
Keyword(s):  
Low Power ◽  
High Speed ◽  
Single Phase ◽  
Average Power ◽  
Circuit Complexity ◽  
Cmos Technology ◽  
Flip Flop ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper the authors came up with a contemporary low power, high-speed 18- transistor true singlephase clocking D flip-flop (FF) design using complementary pass-transistor logic. This design is a master-slave-type logic structure and hybrid logic design consisting of complementary pass-transistor logic style and static CMOS logic style. In order to reduce the number of transistors and to simplify the circuit complexity complementary pass-transistor logic style is used. In this design state transition is faster in the slave latch which enhances time performance using a virtual VDD technique. The circuit is designed using GPDK 90nm CMOS technology and the simulation results show better performance indices such as average power consumption, clock- to-Q delay, data-to-Q delay, PDP and area of utilization.

scholarly journals Low Power based Dynamic TSPC D flip flop for High Performance Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 758-762
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Memory Cell ◽  
Research Center ◽  
Short Channel ◽  
Flip Flop ◽  
Force Application ◽  
Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Sign in / Sign up

Export Citation Format

Share Document