Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits

Author(s):  
Takashi Sato ◽  
Junya Kawashima ◽  
Hiroshi Tsutsui ◽  
Hiroyuki Ochi
1992 ◽  
Vol 27 (4) ◽  
pp. 583-588 ◽  
Author(s):  
Y. Miyawaki ◽  
T. Nakayama ◽  
S. Kobayashi ◽  
N. Ajika ◽  
M. Ohi ◽  
...  

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.


2021 ◽  
Author(s):  
Shailendra Tripathi ◽  
Amit Mahesh Joshi

Abstract This work presents a wide-band active filter for RF receiver. The design uses Carbon Nanotube-FET (CNFET) based differential voltage current conveyor (DVCC) for the implementation of the proposed filter. The filter is designed to operate Ku-band frequencies (12-18 GHz), which is used in satellite communication. Additionally, CMOS based circuit and CNFET-based circuit for DVCC are compared for the performance evaluation. HSPICE simulations have been carried out to test the design aspects of the circuit. The CNFET-based circuit has better results in terms of 60 % reduction in the power consumption and about six times improvement in the bandwidth. The filter utilizes low supply voltage of 0.9 V and consumes 524 µW only. The proposed filter outperforms the existing CMOS-based designs which suggests its usage for low-power high-frequency analog circuits.


Author(s):  
Hongkuan Yu ◽  
Tomoko Mizutani ◽  
Kiyoshi Takeuchi ◽  
Takuya Saraya ◽  
Masaharu Kobayashi ◽  
...  

Abstract Minimum operating voltages (Vmin) of every cell on a 32kb fully-depleted (FD) SOI static random access memory (SRAM) macro are successfully measured. The competing Vmin distribution models, which include the gamma and log-normal distribution, are approximated using the generalized gamma distribution (GENG). It is found that Vmin of the cells follow the gamma distribution. This finding gives a simple method to estimate worst Vmin of an SRAM macro by measuring few samples and make linear extrapolation from the gamma distribution.


Author(s):  
H. T. Manohara ◽  
B. P. Harish

With advancements in computing and communication technologies on mobile devices, the performance requirements of embedded processors have significantly increased, resulting in a corresponding increase in its energy consumption. Dynamic scaling of operating voltage and operating frequency has a strong correlation to energy minimization in CMOS real-time circuits. Simultaneous optimization of ([Formula: see text], [Formula: see text] pairs under dynamic activity levels is thus extensively investigated over several years. The supply voltage is tuned dynamically during runtime (DVS), with a fixed threshold voltage, to achieve energy minimization. This work addresses the issue of maximizing the energy efficiency of real-time periodic, aperiodic and mixed task sets, in a uniprocessor system, by developing a novel task feasibility methodology, with a novel processor performance-based constraint, to generate the optimal operating supply voltage to the individual task of task sets. The energy minimization of real-time mixed task sets is formulated as Geometric Programming (GP) problem, by varying frequency for periodic tasks sets and keeping fixed frequency for aperiodic tasks set, over a range of task sets and hence computing optimal operating voltages. Simulation experiments show energy savings on the cumulative basis of 50%, 38% and 29% for periodic, aperiodic and mixed task sets, respectively, based on the processing timing constraints of task sets.


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