A 2GS/s 14-bit 25dBm OIP3 Current-Steering DAC in 45nm CMOS Technology

2020 ◽  
Author(s):  
Yilun Wang ◽  
Fengjie Wang ◽  
Yaguang Song ◽  
Zhiyu Wang
Keyword(s):  
Cmos Technology ◽  
Current Steering ◽  
Current Steering Dac

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals Design and implementation of 4 bit binary weighted current steering DAC

2020 ◽  
Vol 10 (6) ◽  
pp. 5642
Author(s):  
Jayeshkumar J. Patel ◽  
Amisha P. Naik
Keyword(s):  
Supply Voltage ◽  
Biomedical Application ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Transmission Gate ◽  
Linearity Error ◽  
Current Steering Dac ◽  
Binary Weighted

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

scholarly journals An 8 bit current steering DAC for offset compensation purposes in sensor arrays

2012 ◽  
Vol 10 ◽  
pp. 201-206
Author(s):  
G. Bertotti ◽  
A. Laifi ◽  
E. Di Gioia ◽  
M. Masoumi ◽  
N. Dodel ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Sensor Arrays ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Current Steering ◽  
Worst Case ◽  
Current Output ◽  
Static Power ◽  
Offset Compensation ◽  
Current Steering Dac

Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm2.

scholarly journals A 2 GS/s 14-bit current-steering DAC in 65 nm CMOS technology for wireless transmitter

2018 ◽  
Vol 15 (13) ◽  
pp. 20180509-20180509 ◽  
Author(s):  
Luxun Chang ◽  
Kaijie Ding ◽  
Zhiwei Xu ◽  
Chunyi Song ◽  
Jipeng Li ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Current Steering ◽  
Wireless Transmitter ◽  
Current Steering Dac

Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology

2015 ◽  
Vol E98.C (12) ◽  
pp. 1193-1195
Author(s):  
Yuan WANG ◽  
Wei SU ◽  
Guangliang GUO ◽  
Xing ZHANG
Keyword(s):  
Cmos Technology ◽  
Current Steering ◽  
Current Steering Dac

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450053 ◽  
Author(s):  
FAN XIA ◽  
YIQIANG ZHAO ◽  
GONGYUAN ZHAO
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Differential Nonlinearity ◽  
Spurious Free Dynamic Range ◽  
Source Block ◽  
Current Steering Dac

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

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