Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

2008 ◽  
Vol 43 (12) ◽  
pp. 2967-2976 ◽  
Author(s):  
Sander L. J. Gierkink
2012 ◽  
Vol 33 (7) ◽  
pp. 075004 ◽  
Author(s):  
Haijun Gao ◽  
Lingling Sun ◽  
Xiaofei Kuang ◽  
Liheng Lou

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.


2012 ◽  
Vol 58 (5) ◽  
pp. 425 ◽  
Author(s):  
Harikrishnan Ramiah ◽  
ChongWei Keat ◽  
Jeevan Kanesan

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