Modeling of charge trapping induced threshold-voltage instability in high-/spl kappa/ gate dielectric FETs

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

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Threshold Voltage Instability of Top Gate Single-Crystalline Si Thin-film Transistors on Flexible Substrate Using SiO as Gate Dielectric

ECS Meeting Abstracts ◽

10.1149/ma2007-01/15/723 ◽

2007 ◽

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Flexible Substrate ◽

Single Crystalline ◽

Voltage Instability ◽

Si Thin Film

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Threshold-Voltage Instability in SiC MOSFETs Due to Near-Interfacial Oxide Traps

Materials Science Forum ◽

10.4028/www.scientific.net/msf.858.585 ◽

2016 ◽

Vol 858 ◽

pp. 585-590 ◽

Cited By ~ 1

Author(s):

Aivars J. Lelis ◽

Ronald Green ◽

Daniel B. Habersat

Keyword(s):

Threshold Voltage ◽

Charge Trapping ◽

Test Methods ◽

Device Failure ◽

Voltage Instability ◽

Oxide Trap ◽

Oxide Traps ◽

Trap Activation

There are two basic mechanisms that affect the threshold-voltage (VT) stability: oxide-trap activation and oxide-trap charging. Once additional oxide traps are activated, then they are free to participate in the charge-trapping processes that can, especially for older vintage devices, result in large VT shifts and potential device failure. More recent commercially-available devices show much smaller effects, and minimal trap activation. Given the dramatic improvements, it is now imperative that improved test methods be employed to properly separate out bad devices from good devices.

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Impact of nitrogen in HfON gate dielectric with metal gate on electrical characteristics, with particular attention to threshold voltage instability

Applied Physics Letters ◽

10.1063/1.2709948 ◽

2007 ◽

Vol 90 (10) ◽

pp. 103502 ◽

Cited By ~ 9

Author(s):

Xiongfei Yu ◽

Chunxiang Zhu ◽

Mingbin Yu

Keyword(s):

Threshold Voltage ◽

Gate Dielectric ◽

Electrical Characteristics ◽

Metal Gate ◽

Voltage Instability

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MODELING OF TRAPPING INDUCED THRESHOLD VOLTAGE SHIFT DEPENDENCY ON A TIME-VARYING GATE BIAS IN THIN-FILM TRANSISTORS

Modern Physics Letters B ◽

10.1142/s0217984912501539 ◽

2012 ◽

Vol 26 (23) ◽

pp. 1250153

Author(s):

TAEHO JUNG

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Discrete Model ◽

Gate Dielectric ◽

Thin Film Transistor ◽

Charge Trapping ◽

Time Varying ◽

Threshold Voltage Shift ◽

Exponential Time ◽

Discrete States

The author has developed a discrete model for simulation to calculate the threshold voltage (VT) shift caused by charge trapping and detrapping in a thin film transistor (TFT) under a time-varying bias. The model divides continuous states into discrete states and simplifies tunneling among the discrete states to keep track of their occupancies. The simulation is carried out for a TFT that has traps in the gate dielectric uniformly distributed perpendicular to the semiconductor/dielectric interface and the results account for the stretched-exponential time dependence of VT shift.

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Temperature-Dependence of SiC MOSFET Threshold-Voltage Instability

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.807 ◽

2008 ◽

Vol 600-603 ◽

pp. 807-810 ◽

Cited By ~ 28

Author(s):

Aivars J. Lelis ◽

Daniel B. Habersat ◽

Ronald Green ◽

Neil Goldsman

Keyword(s):

Threshold Voltage ◽

Field Effect ◽

Field Effect Transistors ◽

Temperature Response ◽

Charge Trapping ◽

Gate Bias ◽

Voltage Instability ◽

Increasing Temperature ◽

Mobile Ions ◽

Interfacial Charge

We have observed variations in the instability in the threshold voltage, VT, of SiC metaloxide semiconductor field-effect transistors (MOSFETs) from various sources and/or processes due to gate-bias stressing as a function of temperature. In some cases we see a dramatic increase in the instability with increasing temperature, consistent with interfacial charge trapping or de-trapping. In other cases the temperature response is very slight, and in still other cases we actually see VT instabilities that move in the opposite direction with bias, indicating the presence of mobile ions.

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