Threshold-Voltage Instability in SiC MOSFETs Due to Near-Interfacial Oxide Traps

2016 ◽  
Vol 858 ◽  
pp. 585-590 ◽  
Author(s):  
Aivars J. Lelis ◽  
Ronald Green ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Test Methods ◽  
Device Failure ◽  
Voltage Instability ◽  
Oxide Trap ◽  
Oxide Traps ◽  
Trap Activation

There are two basic mechanisms that affect the threshold-voltage (VT) stability: oxide-trap activation and oxide-trap charging. Once additional oxide traps are activated, then they are free to participate in the charge-trapping processes that can, especially for older vintage devices, result in large VT shifts and potential device failure. More recent commercially-available devices show much smaller effects, and minimal trap activation. Given the dramatic improvements, it is now imperative that improved test methods be employed to properly separate out bad devices from good devices.

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1317-1320 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Linear Increase ◽  
Oxide Semiconductor ◽  
Bias Stress ◽  
Voltage Instability ◽  
Current Voltage ◽  
Oxide Traps ◽  
Charge Tunneling

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).

A Study of High Temperature DC and AC Gate Stressing on the Performance and Reliability of Power SiC MOSFETs

2013 ◽  
Vol 740-742 ◽  
pp. 549-552 ◽  
Author(s):  
Ronald Green ◽  
A.J. Lelis ◽  
M. El ◽  
Daniel B. Habersat
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
State Of The Art ◽  
Temperature Measurements ◽  
Voltage Instability ◽  
Test Methodology ◽  
Full Effect ◽  
Oxide Trap ◽  
Bias Temperature Stress ◽  
Trap Activation

Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.

Temperature-Dependence of SiC MOSFET Threshold-Voltage Instability

2008 ◽  
Vol 600-603 ◽  
pp. 807-810 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
Ronald Green ◽  
Neil Goldsman
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Temperature Response ◽  
Charge Trapping ◽  
Gate Bias ◽  
Voltage Instability ◽  
Increasing Temperature ◽  
Mobile Ions ◽  
Interfacial Charge

We have observed variations in the instability in the threshold voltage, VT, of SiC metaloxide semiconductor field-effect transistors (MOSFETs) from various sources and/or processes due to gate-bias stressing as a function of temperature. In some cases we see a dramatic increase in the instability with increasing temperature, consistent with interfacial charge trapping or de-trapping. In other cases the temperature response is very slight, and in still other cases we actually see VT instabilities that move in the opposite direction with bias, indicating the presence of mobile ions.

Two-Way Tunneling Model of Oxide Trap Charging and Discharging in SiC MOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 465-468 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
Ronald Green ◽  
Neil Goldsman
Keyword(s):  
Threshold Voltage ◽  
Experimental Results ◽  
Measurement Time ◽  
Tunneling Model ◽  
Bias Stress ◽  
Voltage Instability ◽  
Oxide Trap

A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison with experimental results. This model can successfully account for the variation in threshold-voltage instability observed as a function of bias-stress time, bias-stress magnitude, and measurement time.

Quantified Density of Active near Interface Oxide Traps in 4H-SiC MOS Capacitors

2016 ◽  
Vol 858 ◽  
pp. 603-606 ◽  
Author(s):  
Hamid Amini Moghadam ◽  
Sima Dimitrijev ◽  
Ji Sheng Han ◽  
Amirhossein Aminbeidokhti ◽  
Daniel Haasmann
Keyword(s):  
Conduction Band ◽  
Threshold Voltage ◽  
Energy Levels ◽  
New Method ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Voltage Instability ◽  
Capacitance Voltage ◽  
Oxide Traps

This paper presents a new method to quantify near interface oxide traps (NIOTs) that are responsible for threshold voltage instability of 4H-SiC MOSFETs. The method utilizes the shift observed in capacitance–voltage (C–V) curves of an N-type MOS capacitor. The results show that both shallow NIOTs with energy levels below the bottom of conduction band and NIOTs with energy levels above the bottom of the conduction band of SiC are responsible for the C–V shifts, and consequently, for the threshold voltage instabilities in MOSFETs. A higher density of NIOTs is measured at higher temperatures.

Charge Trapping in Sic Power MOSFETs and its Consequences for Robust Reliability Testing

2012 ◽  
Vol 717-720 ◽  
pp. 1085-1088 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Test Methods ◽  
Direct Application ◽  
Reliability Test ◽  
Reliability Testing ◽  
Power Mosfets ◽  
Test Standards ◽  
Device Reliability ◽  
Robust Reliability

Threshold voltage (VT) instability remains an important issue for the performance, reliability, and qualification of SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. To ensure SiC MOSFET device reliability, some modifications to existing test methods may be necessary..

High-Temperature Reliability of SiC Power MOSFETs

2011 ◽  
Vol 679-680 ◽  
pp. 599-602 ◽  
Author(s):  
Aivars J. Lelis ◽  
Ronald Green ◽  
Daniel B. Habersat
Keyword(s):  
Elevated Temperature ◽  
Threshold Voltage ◽  
Vacancy Defect ◽  
Applied Bias ◽  
Power Mosfets ◽  
Device Failure ◽  
Voltage Instability ◽  
Defect Sites ◽  
O Vacancy ◽  
Adequate Margin

We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.

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