MODELING OF TRAPPING INDUCED THRESHOLD VOLTAGE SHIFT DEPENDENCY ON A TIME-VARYING GATE BIAS IN THIN-FILM TRANSISTORS

2012 ◽  
Vol 26 (23) ◽  
pp. 1250153
Author(s):  
TAEHO JUNG

The author has developed a discrete model for simulation to calculate the threshold voltage (VT) shift caused by charge trapping and detrapping in a thin film transistor (TFT) under a time-varying bias. The model divides continuous states into discrete states and simplifies tunneling among the discrete states to keep track of their occupancies. The simulation is carried out for a TFT that has traps in the gate dielectric uniformly distributed perpendicular to the semiconductor/dielectric interface and the results account for the stretched-exponential time dependence of VT shift.

Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 634 ◽  
Author(s):  
Kwon ◽  
Choi ◽  
Bae ◽  
Park

We show that transfer hysteresis for a pentacene thin film transistor (TFT) with a low-temperature solution-processed zirconia (ZrOx) gate insulator can be remarkably reduced by modifying the ZrOx surface with a thin layer of crosslinked poly(4-vinylphenol) (c-PVP). Pentacene TFTs with bare ZrOx and c-PVP stacked ZrOx gate insulators were fabricated, and their hysteresis behaviors compared. The different gate insulators exhibited no significant surface morphology or capacitance differences. The threshold voltage shift magnitude decreased by approximately 71% for the TFT with the c-PVP stacked ZrOx gate insulator compared with the bare ZrOx gate insulator, with 0.75 ± 0.05 and 0.22 ± 0.03 V threshold voltage shifts for the bare ZrOx and c-PVP stacked ZrOx gate insulators, respectively. The hysteresis reduction was attributed to effectively covering hysteresis-inducing charge trapping sites on ZrOx surfaces.


2011 ◽  
Vol 99 (6) ◽  
pp. 062108 ◽  
Author(s):  
Bosul Kim ◽  
Eugene Chong ◽  
Do Hyung Kim ◽  
Yong Woo Jeon ◽  
Dae Hwan Kim ◽  
...  

RSC Advances ◽  
2019 ◽  
Vol 9 (36) ◽  
pp. 20865-20870 ◽  
Author(s):  
Dong-Gyu Kim ◽  
Jong-Un Kim ◽  
Jun-Sun Lee ◽  
Kwon-Shik Park ◽  
Youn-Gyoung Chang ◽  
...  

We studied the effect of X-ray irradiation on the negative threshold voltage shift of bottom-gate a-IGZO TFT. Based on spectroscopic analyses, we found that this behavior was caused by hydrogen incorporation and oxygen vacancy ionization.


2006 ◽  
Vol 937 ◽  
Author(s):  
Chang-Wook Han ◽  
Sang-Geun Park ◽  
Chang-Yeon Kim ◽  
Min-Koo Han ◽  
Gun-Woo Hyung ◽  
...  

ABSTRACTA top gate pentacene TFT employing vapor deposited polyimide as a gate dielectric was fabricated. Polyimide was co-evaporated from 6FDA and ODA monomers and annealed at 150 °C in vacuum. The degree of imidization was verified by FT-IR. A breakdown voltage of 0.9 MV/cm of polyimide film was measured by MIM structure. A top gate pentacene TFT with W/L=25 has 0.01 cm2/Vs as a mobility, about 103 as an on-off ratio (In/off), −7.5V as a threshold voltage and 9 V per decade as a sub-threshold slope.


Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>


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