Impact of Highly Compressive Interlayer-Dielectric-$ \hbox{SiN}_{x}$ Stressing Layer on $\hbox{1}/f$ Noise and Reliability of SiGe-Channel pMOSFETs

2010 ◽  
Vol 31 (12) ◽  
pp. 1368-1370 ◽  
Author(s):  
Yu-Ting Chen ◽  
Kun-Ming Chen ◽  
Wen-Shiang Liao ◽  
Guo-Wei Huang ◽  
Fon-Shan Huang
2003 ◽  
Vol 766 ◽  
Author(s):  
Kenneth Foster ◽  
Joost Waeterloos ◽  
Don Frye ◽  
Steve Froelicher ◽  
Mike Mills

AbstractThe electronics industry, in a continual drive for improved integrated device performance, is seeking increasingly lower dielectric constants (k) of the insulators that are used as interlayer dielectric (ILD) for advanced logic interconnects. As the industry continually seeks a stepwise reduction of the “effective” dielectric constant (keff), simple extendibility, leads to the consideration of the highest performance possible, namely air bridge technology. In this paper we will discuss requirements, integration schemes and properties for a novel class of materials that has been developed as part of an advanced technology probe into air bridge architecture. We will compare and contrast these potential technology offerings with other existing dense and porous ILD integration options, and show that the choice is neither trivial nor obvious.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.


Author(s):  
Hide Murayama ◽  
Makoto Yamazaki ◽  
Shigeru Nakajima

Abstract Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.


2019 ◽  
Vol 3 (12) ◽  
Author(s):  
Stefana Anais Colibaba ◽  
Sabine Körbel ◽  
Carlo Motta ◽  
Fedwa El-Mellouhi ◽  
Stefano Sanvito

2014 ◽  
Vol 14 (1) ◽  
pp. 57-65 ◽  
Author(s):  
Sathyanarayanan Raghavan ◽  
Ilko Schmadlak ◽  
George Leal ◽  
Suresh K. Sitaraman

2004 ◽  
Vol 447-448 ◽  
pp. 580-585 ◽  
Author(s):  
Sang-Bae Jung ◽  
Sung-Woo Park ◽  
Jun-Kyu Yang ◽  
Hyung-Ho Park ◽  
Haecheon Kim

2019 ◽  
Vol 6 (2) ◽  
pp. 213-219 ◽  
Author(s):  
Satoshi Tanimoto ◽  
Hiromichi Oohashi ◽  
Kazuo Arai

2003 ◽  
Vol 216 (1-4) ◽  
pp. 98-105 ◽  
Author(s):  
Sung-Woo Park ◽  
Sang-Bae Jung ◽  
Min-Gu Kang ◽  
Hyung-Ho Park ◽  
Hae-Cheon Kim

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